Authors: A.V-Y. Thean, N. Collaert, N. Waldron, C. Merckling, L. Witters, R. Loo, J. Mitard, R. Rooyackers, A. Vandooren, A. Verhulst, A. Veloso, A. Pourghaderi, G. Eneman, D. Yakimets, T. Huynh Bao, M. Garcia Bardon, J. Ryckaert, M. Dehan, P. Wambacq, M. Caymax
Affilation: IMEC, Belgium
Pages: 1 - 4
Keywords: heterogeneous, nano-electronic devices, monolithic integration, IIIV, Ge, Si, FinFET, TFETs, nanowires
3D-IC’s by stacking and connecting dies of different functions with through-silicon via processes are emerging as an upcoming heterogeneous SOC enabler. Since connectivity between stacked layers may be limited by nearest-neighbor layers, the stagnation of performance/density scaling of the components of the stacked 2-D layers, will again limit the 3-D system scaling in the near future. Hence, there is still strong value proposition to enhance the density and functionality at the transistor/circuit level, especially enabling specialized devices that can be applied to boost specific functionality. At the finest grain, co-integration of high-density heterogeneous transistors has been challenged by ability to combine disparate materials and structures while maintaining low enough complexity and defectivity. This paper will look into the materials, process, device and circuit considerations to enable monolithically-integrated heterogeneous devices.
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