Nanotech 2013 Vol. 2
Nanotech 2013 Vol. 2
Nanotechnology 2013: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational (Volume 2)

Modeling & Simulation of Microsystems Chapter 7

Optimized Topology of an ASIC for Thermal Analysis of Multi-Core Processors

Authors: M. Szermer, L. Kotynia, P. Zajac, M. Janicki, A. Napieralski

Affilation: Lodz University of Technology, Poland

Pages: 524 - 527

Keywords: ASIC, multi-core processor, thermal investigation

The main goal of the paper is to present the optimized ASIC design for the investigation of thermal-coupling among cores in multi-core processors. In short, we designed a dedicated ASIC composed of regular 16x24 heat cell array. The power dissipation in each cell is configurable in a wide range. Therefore, it can be used to emulate the power dissipation in the units of a multi-core processor and produce the resulting temperature distribution in a chip. Due to its flexible structure, the described ASIC allows the investigation of any core topology and fabricated in modern nanometer technologies. For example, it can be used to predict the thermal behavior of 16-core processor fabricated using 16 nm process.

ISBN: 978-1-4822-0584-8
Pages: 808
Hardcopy: $209.95