Authors: M. Janicki, P. Zajac, M. Szermer, A. Napieralski
Affilation: Lodz University of Technology, Poland
Pages: 520 - 523
Keywords: tri-gate transistors, thermal simulation, many core processors, technology scaling
This paper presents the analyses of static and dynamic thermal coupling among microsystem components for technologies based on tri-gate transistors. Simulations were carried out using Green’s function thermal solver based on power trace data computed from BSIM-CGM predictive technology models. The most important conlusion is that, unlike in the case of standard planar technologies, when scaling down the tri-gate devices the thermal coupling between particular modules might decrease what could be beneficial for performance improvement. The final version of the paper will validate simulation results with measurements of a thermal test ASIC.
Nanotech Conference Proceedings are now published in the TechConnect Briefs