Nanotech 2011 Vol. 2
Nanotech 2011 Vol. 2
Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational

Compact Modeling Chapter 10

Drain Induced Barrier Lowering (DIBL) Effect on the Intrinsic Capacitances of Nano-Scale MOSFETs

Authors: M.A. Karim, S. Venugopalan, Y.S. Chauhan, D. Lu, A. Niknejad, C. Hu

Affilation: University of California at Berkeley, United States

Pages: 814 - 817

Keywords: MOSFET, DIBL, negative intrinsic capacitance

MOSFET intrinsic capacitances going negative is a major concern in the compact model community. Negative Intrinsic Capacitances (NIC) can raise non-convergence issues in circuit simulators. In some cases NICs can be explained using physical phenomena. In this work we particularly focus on the gate to drain intrinsic capacitance, CGD. For short channel devices, initially gate/channel charge decreases with increasing drain bias, VD, until a considerable amount of DIBL effect kicks in. Due to barrier lowering at the source side, it is very much likely to have more channel charge with increasing VD and consequently may lead to negative CGD. 2-D TCAD simulation on a simple bulk MOSFET structure has been done to manifest the possibility of this phenomenon.

ISBN: 978-1-4398-7139-3
Pages: 854
Hardcopy: $199.95

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