Nanotech 2010 Vol. 2
Nanotech 2010 Vol. 2
Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational

Compact Modeling Chapter 11

Xsim: Benchmark Tests for the Unified DG/GAA MOSFET Compact Model

Authors: X. Zhou, G.J. Zhu, M.K. Srikanth, S.H. Lin, Z.H. Chen, J.B. Zhang, C.Q. Wei, Y.F. Yan, R. Selvakumar

Affilation: Nanyang Technological University, Singapore

Pages: 785 - 788

Keywords: benchmark tests, compact model, double-gate (DG), gate-all-around (GAA), MOSFET, silicon nanowire (SiNW), unified regional modeling (URM), Xsim

This paper presents benchmark tests of the unified compact model (Xsim) for double-gate (DG) and gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs, which has been developed over the years with the unified regional modeling (URM) approach. The core Xsim model is extended from the bulk-MOS model that encompasses partial- and full-depletion SOI as well as DG/GAA FinFET/SiNW devices, with doping scaling from highly-doped to undoped body. Terminal currents and terminal charges are physically scalable over wide ranges of geometry and structural variations, satisfying the basic model benchmark tests such as Gummel symmetry test (GST), slope-ratio test (SRT), tree-top test (TTT), harmonic-balance test (HBT), as well as transcapacitance symmetry and reciprocity. The ultimate goal of the Xsim model is for unification of MOSFET compact models with various gate, body, as well as source/drain structures and dimensions in one unified core framework for simulating and designing integrated circuits in future generation technologies, including bulk/SOI/FinFET/SiNW or a hybrid of them.

ISBN: 978-1-4398-3402-2
Pages: 862
Hardcopy: $189.95

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