Nanotech 2010 Vol. 2
Nanotech 2010 Vol. 2
Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational

Computational Methods, Simulation & Software Tools Chapter 10

Simulation of Surface and Buffer Trapping Effects on Gate Lag in AlGaN/GaN HEMTs

Authors: K. Horio, A. Nakajima, K. Fujii

Affilation: Shibaura Institute of Technology, Japan

Pages: 693 - 696

Keywords: GaN, HEMT, gate lag, trap, surface state

Two-dimensional simulation of turn-on characteristics of AlGaN/GaN HEMTs is performed in which both buffer traps and sur-face states are considered. It is studied how the so-called gate lag is affected by these factors. It is shown that gate lag due to buffer traps can occur because in the off state where the gate voltage is negative, electrons are injected into the buffer layer and captured by the traps, leading to more negatively charged buffer layer. It is also shown that gate lag due to an electron-trap-type surface state can occur only when electron’s gate tunneling is considered.

ISBN: 978-1-4398-3402-2
Pages: 862
Hardcopy: $189.95