Authors: T-Y Li, C-H Hwang, Y. Li
Affilation: National Chiao Tung University, Taiwan
Pages: 586 - 589
Keywords: nanoscale device, process variation, random dopant fluctuation, SRAM
The magnitude of the intrinsic parameter fluctuations, such as process-variation and random dopant fluctuation, steadily increase with the reduction of device dimensions, and lead to pronounced component mismatch in area constrained circuits such as static random access memory (SRAM), limiting the performance, yield and functionality gains of such circuits from further scaling. Various approaches have been proposed to investigate the process-variation and random dopant effect. However, the dependence of SNM and its fluctuation on transistor’s gate length is not clear yet. In this study, a three-dimensional “atomistic” circuit-device coupled simulation approach is proposed to investigate the process-variation and random dopant induced characteristic fluctuations in planar MOSFET SRAM from 65-nm- to 16-nm-gate length. The result shows that the fluctuation of SRAM dependents on transitor’s gate size. Though the decrease of transistor size can significantly increase the density of memory, the decreased SNM and increased SNM fluctuations of SRAM may limit the use of the smallest manufacturable device sizes in a given technology. To reduce the device variability induced fluctuation in circuit, vertical channel devices such as FinFETs is used. The SNM fluctuation of 16-nm-gate FinFETs is five times smaller than that of planar MOSFETs, which shows the promising characteristics in next generation nanoscale transistor.