Authors: A.P. Karmarkar, V.K. Dasarapu, A.R. Saha, G. Braun, S. Krishnamurthy, X.-W. Lin
Affilation: Synopsys (India) Pvt. Ltd., India
Pages: 833 - 836
Keywords: procee-aware extraction, process variability, compact model
The current industry trends call for smaller devices and decreasing feature sizes with each technology node. The process variability has a significant impact on the device characteristics for deep sub-micron technologies because of the smaller device sizes. In this paper, we will demonstrate process-aware circuit model parameter extraction and design strategies to mitigate circuit performance variation resulting from process variability. CMOS devices are simulated using a 45 nm process flow that uses advanced techniques to achieve the requisite performance. The process parameters with maximum impact on the device characteristics are identified and analyzed. Global parameters are extracted for the 45 nm process. Good agreement between the simulation data and the extracted global model is observed. The global and the process-aware models along with the parameter extraction strategies will be described in detail in the full paper. A ring oscillator circuit will be examined to demonstrate the effects of process variability on circuit performance in the full paper. We will also present methods to build circuit designs that account for the process variability in deep sub-micron technologies. This study will provide an insight into the relationship between fabrication and circuit design.
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