Nanotech 2007 Vol. 1
Nanotech 2007 Vol. 1
Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 1

Lithography and Patterning Chapter 4

Silicon Nanowire Transistors Fabricated by the Mass-Manufacturable, Self-Assembling “Grow-in-Place” Approach

Authors: Y. Shan and S.J. Fonash

Affilation: Pennsylvania State University, United States

Pages: 265 - 268

Keywords: nanowire, transistor, grow-in-place, guiding-nanochannel template, self-assembling, mass manufacturability

Silicon nanowire (SiNW) transistor fabrication, until our work, has had environmental concerns and manufacturing issues arising from the use of a complex process flow involving SiNW growth and harvesting followed by nanowire positioning, aligning and gate/contact formation. In this report, we avoid all these issues by introducing a novel SiNW transistor self-assembling “grow-in-place” fabrication approach. Our approach offers the ability of synthesizing self-positioned/self-assembled SiNW transistors in place directly from the Si source gas with mass-manufacturability potential. A nanochannel template, key to our approach, guides the SiNW during vapor-liquid-solid (VLS) nanowire growth and provides control of nanowire size, number, density, position, orientation, and inter-wire spacing. There are no SiNW harvesting, handling, aligning, assembling and integrating steps in fabricating the resulting transistors. In addition, our nanowire fabrication approach is environmentally benign since the fabricated nanowires are always fixed by the guiding channels and only the exact number of nanowires needed is fabricated. Field emission scanning electron microscope images of single 60nm SiNW transistors resulting from our approach will be shown along with the corresponding nanowire transistor electrical characteristics. The latter show excellent performance including S values of 130 mV/Dec and on/off ratios of 10^6.

ISBN: 1-4200-6182-8
Pages: 726
Hardcopy: $139.95

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