Nanotech 2006 Vol. 3
Nanotech 2006 Vol. 3
Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3

Compact Modeling Chapter 7

High-Voltage LDMOS Compact Modeling

Authors: M.B. Willemsen, R. van Langevelde and D.B.M. Klaassen

Affilation: Philips Research, Netherlands

Pages: 714 - 719

Keywords: LDMOS, high-voltage, compact modeling

In compact modeling of high-voltage LDMOS devices often a sub-circuit approach is used. While for the channel region a standard compact MOS model (for example BSIM4, MM11 or PSP) is used, the drift region is described by a compact JFET model. We will show that using this conventional approach<br>the effects of the widening of the depletion region in the lateral direction can not be taken into account properly.<br>As a consequence the voltage at the internal node between channel and drift region becomes unphysical and accurate<br>physics-based capacitance modeling becomes unfeasible.<br>&nbsp;<br>In this paper we will introduce a new approach for compact LDMOS modeling to remedy these shortcomings. Next we describe the method to implement this approach in a circuit simulator. Finally a comparison of measurements and simulations is presented for both currents and capacitances.

ISBN: 0-9767985-8-1
Pages: 913
Hardcopy: $119.95

2015 & Newer Proceedings

Nanotech Conference Proceedings are now published in the TechConnect Briefs

NSTI Online Community