Authors: F. Guigues, F. Rudolff and E. Kussener
Affilation: L2MP UMR 6137 CNRS - ISEN-Toulon, France
Pages: 864 - 867
Keywords: analog design methodology, EKV MOS model, ultra low power, weak, moderate and strong inversion, MOS sizing
When strong constraints of supply voltage (< 1V ) and bias current (< 100nA) are required, the only way to meet design’s<br>specifications without using huge silicon area consists on decreasing transistor’s inversion level and therefore going in moderate<br>inversion. Gm/Id methodology is a good solution in case of dynamic target, but unusable for static circuits. In this case, analog<br>designers need continuous over inversion level, hand calculation usable equations.<br>EKV 2.0 MOS model proposes current drain formula continuous from weak to strong inversion. This equation is invertible<br>and thus usable for hand calculation, but only when transistors are saturated. The solution proposed to have a conduction drain<br>current expression, continuous from weak to strong inversion and invertible, is to fix a conduction level .<br>Starting from proposed equations, or standard asymptotes when strong constraint of weak/strong inversion are imposed,<br>design’s equations can be found. On the other hand, design’s specifications such as acceptable transistors’ sizes or current<br>bias, permit to fix vectors of solutions for each design’s unknowns. Integration of these vectors and designs’ equations into a<br>mathematical computing software result in the creation of wholes of solutions which describe completely the design.<br>It is thus possible to made a complete study of a static circuit, independent of inversion level so as to make optimum<br>design. Supply voltage and silicium area can be unambiguously optimize, without risk of running in circle as in ”traditional”<br>approaches. Furthermore, it permits to use circuit simulator only for ”final polish”. As a consequence, the study made, changing<br>of technology can be made almost immediately.