Authors: H. Hashempour and F. Lombardi
Affilation: LTX Corp., United States
Pages: 471 - 474
Keywords: nanowire, circuit design, layout optimization, physical area
An strategy for developing integrated circuits with many individual nanodevices has yet to be formulated. This paper presents an homogeneous (array-based) approach for designing and manufacturing digital circuits using nanotubes or nanowires. By targeting contacts which occupy large area, and using a novel high level combinatorial formulation for area, substantial savings is obtained in physical mask layouts. The ultimate objective is to provide a further insight on the applicability of Moore's law to nanotechnology by evaluating the effects of area in logic circuit design.
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