Nanotech 2004 Vol. 3
Nanotech 2004 Vol. 3
Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 3

Characterization and Parameter Extraction Chapter 9

Burned Metal Phenomenon: A Study of Critical Factors and Their Effects on IC Devices during Parallel Lapping

Authors: P. Batteate and J.Y. Liao

Affilation: Nvidia, United States

Pages: 414 - 416

Keywords: IC failure analysis, parallel lapping

Parallel lapping is widely employed in destructive physical analysis on semiconductor integrated circuits, to reveal defects isolated by electrical failure analysis tools and techniques. A clean sample surface is critical so that the analysts can accurately identify the real defects and not be misled by anomalies possibly introduced during deprocessing. Burned metal has been identified as one type of failure mechanism, caused by electrically overstressing the device. Its presence as failure mechanism is usually validated by electrical and circuit analysis. However, in some cases additional burned metal was also observed on areas unrelated to suspect locations. To understand this phenomenon, we carefully examined the procedure of parallel lapping and conducted a series of experiments to determine the cause and effects of critical factors on IC devices during parallel lapping.

ISBN: 0-9728422-9-2
Pages: 561
Hardcopy: $79.95