A Study of the Threshold Voltage Variations for Ultra-thin Body Double Gate SOI MOSFETs

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Double gate silicon on insulator (SOI) devices are more and more attractive for sub-50 nm ultra-large scaled integrated (ULSI) circuits manufacturing. The double gate SOI devices, owing to a difficulty of manufacturing uniformity, suffer fluctuations of silicon and gate oxide thin films. This is important for design and fabrication of the double gate SOI devices, in particular for the applications of ULSI circuits. From the fabrication point of view, the double gate SOI manufacturing may have a 10 % thin film thickness fluctuation. Therefore, threshold voltage variation resulting from this fluctuation becomes an important problem and should be subject to further investigation when exploring important information for circuit designer and device engineer. Besides the thickness discrepancy in the silicon (Si) thin film, the correlations between the gate oxide thickness variations to threshold voltage changes should also be examined. Considering these two non-uniformity properties for the double gate SOI device, we probably can ensure the ability for double gate SOI ULSI circuit design and manufacturing. Various works have recently been proposed for these devices. In this work, we theoretically examine the fluctuation effects of the Si film thickness on the threshold voltage variation. In the numerical simulation of the threshold voltage variation, the classical and quantum correction transport models, the drift-diffusion (DD) and density gradient (DG) models are considered and solved numerically. Comparing with the classical simulation, the quantum correction way explores different deviation quantitatively. Therefore, a carefully quantum correction should be taken into considerations for avoiding any under- or over-estimations. To clarify the dependence of VTH variation on the fluctuation of Si film thickness, the DG simulation is performed for different film thicknesses and doping concentrations. It is found that film thickness decrease, VTH variation increases (~ 30 % for Tsi = 20 nm), and its variation is nonlinear dependency relation. Therefore, this effect must be taken into account for the realization of double gate SOI ULSI circuit.

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Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: March 7, 2004
Pages: 145 - 148
Industry sector: Advanced Materials & Manufacturing
Topic: Informatics, Modeling & Simulation
ISBN: 0-9728422-9-2