Nanotech 2004 Vol. 3
Nanotech 2004 Vol. 3
Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 3

Nanoscale Electronics and Quantum Devices Chapter 2

Translating the Integration Challenges to Molecular Device Requirements - Analysis of Scaling Constraints in Molecular Random Access Memories

Authors: C.J. Amsinck, N.H. Di Spigna, D.P. Nackashi and P.D. Franzon

Affilation: North Carolina State University, United States

Pages: 61 - 64

Keywords: molecular electronics, random access memories, scalability, device integration, molecular memory

Integrating molecular memory devices into large scale arrays is a key requirement for translating the miniature size of molecular devices into ultradense memory systems. This in turn imposes constraints on the individual molecular memory devices. A circuit theory approach is used to derive a general parameterized memory circuit model, from which quantitative relationships between the device on:off ratio, noise margin and memory size are studied. Assuming a small interconnect impedance and a reasonable noise margin, a 7:1 on:off ratio would be sufficient for a 4kbit memory, while a 16kbit memory would require a 13:1 ratio. Parasitic impedances become significant in architectures employing molecular interconnect, and full-scale memory circuit simulations are presented as a case study. This way, trends for the impact of all system parameters on system scalability are examined.

ISBN: 0-9728422-9-2
Pages: 561
Hardcopy: $79.95