Authors: P.B.Y. Tan, A.V. Kordesch and O. Sidek
Affilation: Silterra Malaysia, Malaysia
Pages: 191 - 194
Keywords: analog-to-digital converter, half-flash, CMOS, simplified method, voltage estimator
In this paper, we present a simplified method to construct a half-flash analog-to-digital converter (ADC) to achieve less die area consumption compared to the conventional half-flash ADC. Although the die area consumption is reduced but the conversion speed can still be maintained about the same as the conventional half-flash ADC. The simplified half-flash ADC performs two fullflash cycles as the conventional type but with the help of a voltage estimator (VE), the number of comparators used can be reduced up to 80 percent for 8-bit resolution ADC and more than 80 percent for higher resolution. This is because the VE can predict roughly the range where the input voltage, Vin resides on the resistor ladder and comparators are only placed at the predicted range. The major reduction in comparators count is the main factor that enables us to achieve less die area consumption.
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