2007 NSTI Nanotechnology Conference and Trade Show - Nanotech 2007 - 10th Annual

Modeling Process Variations Using a Compact Model

R. Murali and J.D. Meindl
Georgia Tech, US

gate length variation, short channel effect, delay distribution, yield

Inclusion of manufacturing variations has become an important part of static timing analysis. Existing statistical timing analysis methods involve the use of time-consuming circuit simulations or use fit polynomials. Previous efforts at modeling parameter variations have yielded equations that are not closed-form and might require numerical solutions. In this work a compact model is derived to predict the effect of manufacturing variations on the delay distribution of circuits. The model is physics-based, shows excellent match with simulations, and is valid over a wide range of device parameters. The model can be used to rapidly assess the impact of various circuit and device parameters on delay variation and thus is a useful tool for design-for manufacturing (DFM) as well as design space exploration.

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