Nanotechnology Conference and Trade Show - Nanotech 2006
> Program > Technical Conferences > Business & Development > Nano Impact Workshop > Nanotech Job Fair > Expo
Index of Authors
Index of Keywords
Confirmed Speakers
Conferences & Symposia

Conference Proceedings

Conference Technical Proceedings

A Charge-Based Compact Model of Double Gate MOSFET

A.S. Roy, C.C. Enz and J.M. Sallese

double-gate, MOSEFT, SOI

To date, a simple physical compact model is still lacking even for the ‘classical’ asymmetric DG MOST because of it’s relatively complex electrostatics. Ref [1] has presented an exact solution for symmetric DG MOST but it does not yield a closed form solution for the drain current for the asymmetric case. This is nevertheless the only approach which can provide drain current for an asymmetric MOST with a good accuracy. The main purpose of this work is to eliminate the need for the numerical integration required in [1] to solve two coupled non-linear equations at each discretization point. At the end, only the source and the drain end charges have to be solved numerically instead of solving it at all the discretization points along the channel. In this work we first prove that a symmetrical relation between common mode gate voltage and channel potential exists for a DG MOST. This feature is unique to the DG MOST in contrast to the bulk MOST and will be used to obtain a closed form expression of the drain current. We will show that due to this symmetry, it is possible to describe the non-equilibrium transport of the DG MOST in terms of its equilibrium relations. Then we will handle the equilibrium electrostatics in a piece-wise way and by suitable interpolation we will propose a semi-empirical analytic closed form charge-based expression for the drain current for both symmetrical and asymmetrical operation. Both charge and current are obtained through a coherent picture using only the physical parameters of the device and a good matching with exact numerical solution over a wide range of bias and geometry is obtained. In addition, due to its special approach based on a novel interpolation technique, this model can also be extended to small-signal parameter analysis, which is mandatory for an efficient circuit design strategy.
[1] Y. Taur, X. Liang, W. Wang, and H. Lu, “A continuous, analytic drain-current model for DG MOSFETs,” IEEE Electron Dev. Let., vol. 25, no. 2, pp.399–401, Feb. 2004.

Back to Program

Sessions Sunday Monday Tuesday Wednesday Thursday Authors

Nanotech 2006 Conference Program Abstract

Nanotechnology Conference | Terms of use | Privacy policy | Contact | NSTI Home
Program | Technical Conferences | Business & Development | Nano Impact Workshop | Nanotech Job Fair | Expo |
Nanotech 2006 Home | Press Room | Venue | Subscribe | Site Map
Names, and logos of other organizations are the property of those organizations and not of NSTI.
This event is not open to the general public and NSTI reserves the right to refuse admission and participation to any individual.