Authors: N. Lu, T.B. Hook, J.B. Johnson, C. Wermer, C. Putnam, R.A. Wachnik
Affilation: IBM, United States
Pages: 548 - 551
Keywords: resistance modeling, schematic transistor model, pre-layout FET model, parasitic resistance and capacitance of FETs, finFET drain current, finFET modeling
We present a schematic transistor model for multi-finger multi-fin FETs, which reduces an initial complex finFET network to a very simple finFET network. The schematic finFET model is accurate in predicting overall finFET characteristics, including the effect of parasitic resistance (R) and capacitance (C) in a finFET. The schematic model also accepts various finFET layout information. Several major semiconductor companies have recently announced plans to manufacture semiconductor chips using finFETs at leading edge semiconductor nodes. Accurate models of finFET parasitic elements are critical. In this paper, we show how to reduce a complex SPICE netlist of a multi-finger multi-fin FET to a very compact SPICE netlist which includes one transistor model call, one source-side parasitic resistive element, one drain-side parasitic resistive element, one gate element, and six parasitic capacitive elements among the source, drain, gate, and substrate nodes of the multi-finger multi-fin FET. We have developed a schematic transistor model for a multi-finger multi-fin FET. This model is used in IBM’s 14nm finFET technology PDKs (process design kits).