Authors: N. Ashraf, S. Joshi, D. Vasileska
Affilation: ASU, United States
Pages: 455 - 458
Keywords: reliability, RTN, RDF
Previously we have reported threshold voltage fluctuations caused by presence of random distribution of dopant ions in the channel region of a 45 nm n-MOSFET and random single interface trap positioned from source to drain of the same channel length n-MOSFET. Subsequently we reported analytical model expressions utilized to assess the threshold voltage fluctuations trends observed by accurate 3D Ensemble Monte Carlo (EMC) simulations performed for 45 nm gate length and 50 nm gate width device. From the knowledge of random telegraph noise (RTN) based device physics, it can be speculated that as the gate width and the channel length are increased, the rather significantly higher fluctuations, observed from threshold voltage shift in presence of random interface trap and random channel dopants, tend to decrease to manageable level aiding in reliable device performance for both analog and digital ICs with long-term operational characteristics. In this paper, we have performed 3D EMC simulation work on a 70 nm gate length and 90 nm gate width n-MOSFET device with random channel dopant and interface trap placements and the results of our simulations strongly support the claim narrated in the above speculations on device scaling based RTN impact on the threshold voltage variability.