Authors: F. Gao, Z. Gu, S. Shina, G. Morose, P. Eliason, R. Farrell
Affilation: University of Massachusetts Lowell, United States
Pages: 422 - 425
Keywords: nanosoldering, nanowires, self-assembly, solder reflow, electronics assembly, packaging
The current demand for high-performance interconnects in advanced packaging is resulting in dramatic scaling down of the electronics packaging feature size from microscale to nanoscale. Novel and/or enhanced interconnection and packaging techniques have to be developed to meet a variety of needs for device or system level integration. Nanosolder-based joining and interconnection techniques provide an opportunity to form robust joints between nanostructures and to integrate nanocomponents into a functional device or complex systems. The approach of nanosoldering has been shown to be effective in the construction of functional and interconnected nanostructures from nanomaterials by utilizing a nanosolder reflow process (see Figure 1A), where the surface oxidation and wettability are critical factors. In this study, the usage of a vapor phase-based fluxing process demonstrates the efficiency of cleaning nanosolder surface oxides and ensuring good nanosolder reflow. A multi-segmented nanowire system, as model one-dimensional nanostructure, provides a good structure to study the intermetallic diffusion and wetting properties of nanosolder systems. In addition, we will show the interaction of nanosolders with different metallic surfaces, such as gold, copper and nickel, as well as the effect of using several industrially relevant fluxes. These measurements will provide the base for developing the nanosoldering techniques and their potential applications in nanomaterial assembly and nanodevice fabrication. These nanosoldering techniques, in combination with one or more assembly techniques that have been developed, will have the great potential not only in nanoscale assembly and nanoscale ball grid array (BGA) formation (see Figure 1B), but also in the integration of sophiscated sensor arrays and the enabling of nanoscale integrated circuits.