Authors: H-W Cheng, C-H Hwang, Y. Li
Affilation: National Chiao Tung University, Taiwan
Pages: 609 - 612
Keywords: multi-fin transistor, nanoscale device, aspect ratio
For nano-CMOS device design, the device with multiple-fin structure has the superior short channel effect (SCE), high driving current and has been considered as an index as potential candidates. The feasibility of various multi-fin options is an emerging challenge. Unfortunately, attention is less draw on investigation the structure effect of multiple-fin transistor. This study explores the electrical characteristics of nanoscale multi-fin FETs with different fin AR. Results show the better fluctuation suppression ability of multi-fin transistors than single-fin transistor. The threshold voltage fluctuations of triple-fin FinFET, tri-gate, and quasi-planar transistors are 4.4, 1.73, and 1.94 times smaller than the single-fin structures. Moreover, the multi-fin FinFETs (AR = 2) exhibit a better channel controllability, smaller external resistance, and layout efficiency than tri-gate and quasi-planar FETs. For multi-fin transistors with 16-nm-gate length and width, the subthreshold swing of FinFETs (AR = 2) is 1.3 and 1.8 times smaller than tri-gate (AR = 1) and quasi-planar (AR = 0.5) FETs. The better channel controllability of FinFETs also implies its better resistance against process variation effect. Moreover, to design a device with subthreshold swing less than 70 mV/dec, the layout area of FinFETs is 1.67 and 1.33 times smaller than that of quasi-planar and tri-gate structures. This multi-fin FinFET with better short channel effect controllability and layout efficiency is promising in next generation nanoscale transistor and system.