Authors: M. Bopp, P. Coronel, F. Judong, K. Jouannic, A. Talbot, D. Ristoiu, C. Pribat, N. Bardos, F. Pico, M.P. Samson, P. Dainesi, A.M. Ionescu, T. Skotnicki
Affilation: Ecole Polytechnique Fédérale de Lausanne, Switzerland
Pages: 634 - 637
Keywords: silicon high temperature annealing, hard mask, buried cavity, Independant double gate transistor
Annealing silicon at high temperatures in hydrogen ambiance has been reported to induce surface diffusion of silicon; in these conditions, adapted 2D arrays of trenches etched in Bulk Si are transformed into buried cavities creating suspended membranes. A 3D nanostructuration of silicon through hard mask engineering and high temperature annealing in hydrogen ambiance is reported. By using a nitride-oxide hard mask stack instead of a sacrificial oxide hard mask for a free surface (maskless) annealing, we open new technological and design possibilities using 2D arrays of various geometry trenches. Implications and potential device applications are discussed.