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 | Nanotech 2007 Vol. 3
Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 7: Compact Modeling |
| | A Setup for Automatic MOSFET Mismatch Characterization under a Wide Bias Range | | Authors: | H. Klimach, C. Galup-Montoro and M.C. Schneider | | Affilation: | Federal University of Santa Catarina, BR | | Pages: | 662 - 665 | | Keywords: | mismatch, test chip, electrical characterization, test structure | | Abstract: | Mismatch is the denomination of time-independent variations between identically designed components. In analog circuits, the spread in the dc characteristics of supposedly matched transistors results in inaccurate or even anomalous circuit behavior. Also, for digital circuits, transistor mismatch leads to propagation delays whose spread can be of the order of several gate delays for deep-submicron technologies. The stochastic nature of the local mismatch of MOS transistors makes their electrical characterization a very complex task. A large number of samples, having different geometries, must be measured under a wide range of bias conditions, in order to characterize device behavior and extract statistical model parameters. In this paper we describe a low-cost MOSFET mismatch characterization setup. It is mainly composed of a test chip that contains 648 pairs of transistors for dc mismatch measurement, where the device selection hardware is placed inside the chip through the use of analog CMOS switches and a serial loading register. This circuit was successfully fabricated and characterized in the TSMC 0.35 um and in the TSMC 0.18 um bulk technologies. | | ISBN: | 1-4200-6184-4 |
| Pages: | 732 |
| Hardcopy: | $199.99 |
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