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 | Nanotech 2007 Vol. 3
Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 3: Sensors & MEMS |
| | The Logical Elements And/ Or are Established on the Elements with Punch-Through and Deformation Space Charge Regions | | Authors: | I. Mats | | Affilation: | Diatex, Selected Texno-Fix, CA | | Pages: | 209 - 212 | | Keywords: | design, logical elements, punch-off, punch-reach, punch-through, space charge | | Abstract: | In this article is proposal a design of logical elements AND/OR based on punch-through effect with a deformation (element AND) of space charge regions (SCR). I.On the substrate N- type is formed P+ - bodies 1 injector and 2 operating elements. By supplying negative voltage equal punch-through voltage (Upt) on one element 2 is occurred punch-through SCRs into P+-N-P+ - structure (injector1 through load resistor is grounded terminal). After punch-through in the device is appeared through current and on the load resistor is assigned a signal. The same process is repeated with other operating element 2. We have logic operation AND. The length d1 is defined from two conditions: d1< d2; d2 > 2[2eeo(jc + Upt)/qNd]1/2 In this case operating signals elements 2 do not interaction between itself. II.Lengths d1 and d2 are changed in logical element OR: d1> d2; d2 < 2[2eeo(jc + Upt)/qNd]1/2 By supplying only one operating signal Upt to the element 2, punch-through process is not occurred between bodies 1 and 2, so d1>d2. By applying two negative operating signals simultaneously is happened punch off process (like in JFET between top and bottom gates) between elements 2 and so d1> d2 beginning displacement their space charge regions, both SCRs get the SCR of injector-substrate p-n junction. The punch-through process gets beginning and on load resistor is allocated a signal. The logical element OR is done. | | ISBN: | 1-4200-6184-4 |
| Pages: | 732 |
| Hardcopy: | $199.99 |
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