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 | Nanotech 2007 Vol. 3
Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 3: Sensors & MEMS |
| | An Architecture of Quantum CPU | | Authors: | V. Téllez, A. Campero, C. Iuga and G. Duchen | | Affilation: | Universidad Autonoma Metropolitana, MX | | Pages: | 205 - 208 | | Keywords: | quantum, central processing unit, Von Neuman | | Abstract: | We present a quantum CPU (central processing unit) which is based on the quantum gate set. Using the Von Neuman model, the quantum CPU has development on a classical Digital Signal Processor (DSP TI6711). The DSP simulated different gates, as the Feynman gate, and the set of the different gates make possible the quantum CPU. Generically, hardware of the quantum CPU are modeled in terms of quantum spins (qubits) that evolve in time according to the time-dependent Schrodinger equation (TDSE). Furthermore, we will try quantum error-correcting code to fight de coherence and operational errors. | | ISBN: | 1-4200-6184-4 |
| Pages: | 732 |
| Hardcopy: | $199.99 |
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