Seebacher E., Posch W., Molnar K., Huszka Z.
austriamicrosystems AG, AT
Keywords: compact modeling, HV MOS transistor, mismatch, SPICE sub-circuit
In this paper we discuss state of the art and new developments of analog modeling for HV CMOS technologies. We will give a detailed overview about the full characterization of a 0.35um high voltage process for analog/HV application. We describe the SPICE modeling of a HV MOS transistor with a sub-circuit including quasi-saturation effect, geometry scaling, lateral doping and parasitic substrate current effects. Additionally a proper mismatch model for HV CMOS transistors including an efficient parameter extraction strategy will be shown.
Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: May 7, 2006
Pages: 720 - 723
Industry sector: Sensors, MEMS, Electronics
Topic: Compact Modeling
ISBN: 0-9767985-8-1