Authors: Z. Jin, Y-M Lee, J.S. Watts, A.R. Bonaccio, G.J. Schroer and N.G. Pai
Affilation: IBM, United States
Pages: 839 - 841
Keywords: mismatch, CMOS, BSIM, op-amp, SRAM
As technology scales, mismatch between a pair of transistors becomes a more and more critical issue for technology development and circuit designs. Scaling also increases the complexity of compact device modeling. Sophisticated models are usually required to capture various device aspects and behaviors associated with scaling, however, they often slow down simulations. Therefore, efficient device models are highly desired, and this efficiency lies in the balance between circuit simulation accuracy and model complexity. In this work, we proposed a simple yet accurate mismatch model based on sensitivity analysis. We compared the circuit simulation results from a SRAM cell and an Op-Amp using the proposed model and our previous model in , and found that the proposed model is accurate enough to predict the circuit performance while it maintains simple enough for fast circuit simulations.