The Design of a Silicon Wire DRAM Cell for Very Dense DRAM Architectures

Bindal A., Aflatooni K.
San Jose State University, US

Keywords: DRAM, nano-wire, silicon wire, vertical FET

In this study, we propose a new DRAM cell that uses a silicon-wire pass transistor stacked on top of a high-dielectric capacitor rated of holding industry-standard 32 fCoulomb charge. We show that the performance of the transistor and the characteristics of the DRAM cell are comparable with those reported in the literature.

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Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: May 8, 2005
Pages: 244 - 247
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topic: Nanoelectronics
ISBN: 0-9767985-2-2