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 | Nanotech 2005 Vol. 3
Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 3: Nano Devices and Architectures |
| | Single-Crystal Nanowire Transistor for Logic and Memory Applications | | Authors: | B. Yu, L. Ye and M. Meyyappan | | Affilation: | NASA Ames Research Center, US | | Pages: | 232 - 235 | | Keywords: | transistor, CMOS, logic, memory, nanowire | | Abstract: | In this paper we report chemical synthesis, device fabrication, and device physics investigation of 1-D single-crystalline nanowire field-effect transistor (SNW-FET) for logic and memory applications. Wafer-scale transistor arrays were fabricated with semiconducting nanowires serve as active channel (for logic) or signal read-out route (for memory). It is demonstrated that the single-crystal nanowire transistor, due to its unique structural features, can be served for high on-off ratio logic switching with superior scalability and data storaging. Device physics study is presented, focusing on ambipolar channel conducting, subthreshold behavior, parasitic resistance, carrier mobility, low-barrier metal-semiconductor Schottky junctions, and performance figure-of-merit analysis. The feasibility of extending the bottom-up fabricated nanowire transistors into sub-10nm CMOS technology is evaluated. | | ISBN: | 0-9767985-2-2 |
| Pages: | 786 |
| Hardcopy: | $165.00 |
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