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 | Nanotech 2005 Vol. 3
Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 11: Modules and Circuits |
| | Fault Tolerant Quantum Computation with new Reversible Gate | | Authors: | D.P. Vasudevan, P.K. Lala and J.P. Parkerson | | Affilation: | University of Arkansas, Fayetteville, US | | Pages: | 744 - 747 | | Keywords: | quantum computing, quantum error correcting codes, fault tolerance, reversible Logic | | Abstract: | Current CMOS technology will be promising only for the next two decades or less until it reaches its physical limit. Once the atomic level of system design comes to the road of technology, Quantum mechanics sounds positive for computation models to be incorporated in the design. Several computational processes that are exponentially time consuming can be achieved in lesser time with quantum computation. But the unreliable physical implementation of the system is acting as the main barrier for the reliable quantum computer design. The quantum information seems to be lost at every step of computation due to the physical processes like Decoherence, Interference etc., But fault tolerant system design seems to be promising field to aid the design of reliable quantum computer. Quantum Error Correcting Codes are being developed to implement fault tolerant quantum computer. Several elementary quantum gates are being constructed which can form the basic building block of fault tolerant quantum computers. This paper deals with the construction one of such elementary quantum gate. | | ISBN: | 0-9767985-2-2 |
| Pages: | 786 |
| Hardcopy: | $165.00 |
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