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 | Nanotech 2005 Vol. 3
Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 10: Computational Methods, Numerics and Software Tools |
| | Investigation of Local-Strain Effect of the Nano-Scale Triple Gate Si/SiGe and SiN/Si Stacking MOS Transistor | | Authors: | C.H. Chang, C.Y. Chou, C.T. Peng, C.N. Han and K.N. Chiang | | Affilation: | National Tsing-Hua University, TW | | Pages: | 688 - 691 | | Keywords: | tri-gate CMOS transistor, highly-tensile silicon nitride, strained silicon, SiGe, nano | | Abstract: | The tensile strained Si, based on the misfit between Si and SiGe gives higher speed and higher drive current for the metal oxide silicon field effect transistors. Based on the strained Si technology, a tri-gate CMOS transistor is further applied in the current leakage control and chip performance enhancement. Moreover, the “highly-tensile” silicon nitride capping layer is also applied for the strained Si applications, the stress from the silicon nitride capping layer is uniaxially transferred to the NMOS channel through the source-drain region to create tensile strain in NMOS channel. | | ISBN: | 0-9767985-2-2 |
| Pages: | 786 |
| Hardcopy: | $165.00 |
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