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 | Nanotech 2005 Vol. 3
Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 1: Nanoscale Device and Process Modeling |
| | A Distributed Compact Model for High-Density, On-Chip Trench Capacitors in High-Frequency Applications | | Authors: | S. Shastri, Y. Wu, W.Z. Cai and G. Grivna | | Affilation: | ON Semiconductor, US | | Pages: | 119 - 122 | | Keywords: | compact model, trench capacitor, series resistance, frequency, voltage, temperature | | Abstract: | In this paper we describe for the first time a distributed model for the trench capacitor, which includes process parameters that may be extracted from the low-frequency measurement of one or two capacitor geometries. The model is then correct by construction for all geometries and layouts of interest. Despite its sophisticated nature, the distributed model does not impose a significant computational burden. Leakage current is low and the Voltage-dependence of the low-frequency capacitance is very small. The temperature dependence is linear and small. In summary, the capacitance is given as C = Co(np, nf, f) * (1 + a(T-To)) * (1+a1V+a2V2), where a=0.63/°C, To=0°C, a1=525ppm/V and a2=-52ppm/V2 for the capacitors considered in this work. Note that Co(np, nf, f) has no analytical solution, but is described in Fig.s 3-6. | | ISBN: | 0-9767985-2-2 |
| Pages: | 786 |
| Hardcopy: | $165.00 |
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