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 | Nanotech 2005 Vol. 3
Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 1: Nanoscale Device and Process Modeling |
| | Mismatch Improvement with XMOS Structure | | Authors: | P.B.Y. Tan, A.V. Kordesch and O. Sidek | | Affilation: | Silterra Malaysia Sdn Bhd, MY | | Pages: | 53 - 56 | | Keywords: | mismatch, matching, XMOS, MOS, transistor performance | | Abstract: | MOS transistor has been continuously scaled down to improve the device performance. Smaller MOS transistors have higher transconductance (gm) and low capacitance, so the ratio gm/C is improved by shrinking. Shorter gate length provides higher drain current which improve the transistor switching speed. Mismatch is one of the major barrier for device downscaling, especially for analog designers. Mismatch and transistor size always contradict each others. According to inverse square root area law, mismatch increases when transistor size decreases. This means that it is almost impossible to improve the transistor performance (by shrinking the gate length) and to improve the transistor mismatch at the same time. In this paper, we propose a method of constructing the gate structure that will improve both the transistor performance and the transistor mismatch at the same time. The structure that we proposed is Cross MOS (XMOS) structure. The XMOS structure has a cross gate that provide extra channel width and extra gate area that gives higher transistor performance and better transistor matching. But no increase in source/drain parasitic capacitance. | | ISBN: | 0-9767985-2-2 |
| Pages: | 786 |
| Hardcopy: | $165.00 |
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