| |
 | Nanotech 2004 Vol. 2
Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 2
Chapter 4: Circuits |
| | Scalability and High Frequency Extensions of the Vector Potential Equivalent Circuit (VPEC) | | Authors: | B. Mukherjee, P. Wang, L. Wang and A. Pacelli | | Affilation: | Stony Brook University, US | | Pages: | 199 - 202 | | Keywords: | inductance, interconnects, circuit extraction | | Abstract: | We present a complete modeling technique for inductive parasitics, based on the vector potential equivalent circuit (VPEC) topology. Novel algorithms for layout extraction and sparsification are introduced. Examples are discussed in terms of CPU time, accuracy, and model complexity. Finally, extensions for high frequency applications are presented, including models for skin effect and full wave simulation. | | ISBN: | 0-9728422-8-4 |
| Pages: | 519 |
| Hardcopy: | $150.00 |
|
| Order: | Mail/Fax Form |
| Special: | 3 CD Set — 15% off with Free Shipping |
| Up | |
|
| nanoPRwire™ |
 |
| News Headlines |
 |
|
|
| |
| |
|
| | |
| |
|
|
