| |
 | Nanotech 2004 Vol. 2
Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 2
Chapter 3: Compact Modeling |
| | Floating Gate Devices: Operation and Compact Modeling | | Authors: | P. Pavan, L. Larcher and A. Marmiroli | | Affilation: | Università di Modena e Reggio Emilia, IT | | Pages: | 120 - 123 | | Keywords: | compact model, nonvolatile memory, floating gate, reliability, circuit design | | Abstract: | This paper describes a possible approach to Compact Modeling of Floating Gate devices. Floating Gate devices are the basic building blocks of Semiconductor Nonvolatile Memories (EPROM, EEPROM, Flash). Among these, Flash are the most innovative and complex devices. The strategy followed developing this new model allows to cover a wide range of simulation conditions, making it very appealing for device physicists and circuit designers. | | ISBN: | 0-9728422-8-4 |
| Pages: | 519 |
| Hardcopy: | $150.00 |
|
| Order: | Mail/Fax Form |
| Special: | 3 CD Set — 15% off with Free Shipping |
| Up | |
|
| Upcoming Events |
 |
 |
 |
 |
| nanoPRwire™ |
 |
| News Headlines |
 |
|
|
| |
| |
|
| | |
| |
|
|
