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 | Nanotech 2004 Vol. 1
Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 1
Chapter 11: Wafer and MEMS Processing |
| | Planarize the Sidewall Ripples of Silicon Deep Reactive Ion Etching | | Authors: | K-Y Weng, M-Y Wang and P-H Tsai | | Affilation: | Industrial Technology Research Institute, TW | | Pages: | 473 - 476 | | Keywords: | silicon deep RIE, sidewall roughness | | Abstract: | In order to diminish the sidewall defects in silicon deep reactive ion etching process, depositing doped silicon dioxide and post-annealing processes are applied. Compared with conventional approaches, the filling-reflow surface shows nearly optical quality. the sidewall roughness of different schemes is compared by cross-section views of scanning electron microscope, shown in the figure 3 and 4 and the ripples are successfully diminished. Atomic force microscopy, AFM, measurement shows 77 and 22 nm in the etched structure and 37 and 8 nm for the PSG-deposited structures, respectively peak-to-valley difference and root mean square. The unique integrated processes expect to implement in the micro devices or replica master with optical surfaces. | | ISBN: | 0-9728422-7-6 |
| Pages: | 521 |
| Hardcopy: | $150.00 |
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