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 | Nanotech 2003 Vol. 2
Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2
Chapter 7: Compact Modeling |
| | A Compact Model Methodology for Device Design Uncertainty | | Authors: | R. Williams, J. Watts, M-H Na, K. Bernstein | | Affilation: | Internatoinal Business Machines Corporation, US | | Pages: | 334 - 337 | | Keywords: | compact model, concurrent design, product design, transistor design, constrained performance, monte carlo, circuit simulation | | Abstract: | Todays ULSI chip and transistor technologies have a high degree of concurrency due to the complexity of new, advanced high performance features. This creates challenges for circuit designer who must account for the evolution of the transistor design while developing their chip design. This work describes for the first time a compact model methodology that gives the circuit designer the ability to assess the impact of uncertainty in the transistor design. |  | View paper | | ISBN: | 0-9728422-1-7 |
| Pages: | 600 |
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