Williams R., Watts J., Na M-H, Bernstein K.
Internatoinal Business Machines Corporation, US
Keywords: circuit simulation, compact model, concurrent design, constrained performance, Monte Carlo, product design, transistor design
Todays ULSI chip and transistor technologies have a high degree of concurrency due to the complexity of new, advanced high performance features. This creates challenges for circuit designer who must account for the evolution of the transistor design while developing their chip design. This work describes for the first time a compact model methodology that gives the circuit designer the ability to assess the impact of uncertainty in the transistor design.
Journal: TechConnect Briefs
Volume: 2, Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2
Published: February 23, 2003
Pages: 334 - 337
Industry sector: Sensors, MEMS, Electronics
Topic: Compact Modeling
ISBN: 0-9728422-1-7