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 | Nanotech 2003 Vol. 2
Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2
Chapter 7: Compact Modeling |
| | A Surface-Potential-Based Compact Model of NMOSFET Gate Tunneling Current | | Authors: | X. Gu, H. Wang, G. Gildenblat, G. Workman, S. Veeraraghavan, S. Shapira and K. Stiles | | Affilation: | Penn State University, US | | Pages: | 318 - 321 | | Keywords: | gate tunneling current, surface potential, MOSFET, compact model | | Abstract: | The continued aggressive scaling of the gate oxide thickness makes the accurate modeling of the gate tunneling current an important aspect of the MOSFET compact model. This work presents a new compact model of which is valid in all operation regions and is surface-potential based in both the channel and overlap regions. The total gate current is presented as a sum of three components from the overlap regions and from the channel area. The physical modeling of the overlap regions is particularly important as they contribute a significant fraction of in scaled devices. This approach is made practical by a newly developed analytical approximation for the surface potential in the overlap regions. Excellent fit of the back and drain bias dependence of is achieved by employing the Esaki-Tsu supply function to describe the difference of carrier populations across the gate oxide. Consequently, the physically meaningful result is achieved without imposing any artificial multiplication factor often required in the existing compact models. |  | View paper | | ISBN: | 0-9728422-1-7 |
| Pages: | 600 |
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