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 | Nanotech 2003 Vol. 2
Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2
Chapter 7: Compact Modeling |
| | Modeling of Direct Tunneling Current in Multi-Layer Gate Stacks | | Authors: | M.V. Dunga, X. Xi, J. He, I. Polishchuk, Q. Lu, M. Chan, A. Niknejad and C. Hu | | Affilation: | University of California, Berkeley, US | | Pages: | 306 - 309 | | Keywords: | gate stack, direct tunneling | | Abstract: | Device scaling to improve performance calls for reduction of the gate oxide thickness but at a cost of increased direct tunneling gate current. The ITRS 2001 recognizes the need of gate scaling below 2nm and hence the use of high-k dielectric gate stacks to reduce gate leakage. It also recognizes the need of gate stack models for ultra-thin dielectrics to help the design of dielectric stacks. Numerical methods exist to solve for direct tunneling through dielectric stacks using Schrödinger’s equation. In this work, a simple analytical model for direct tunneling gate leakage in multi-layer gate stacks is developed. Theoretical derivation is done to show that the current BSIM equation for direct tunneling gate current through a single layer also works for the multi-layer case. Experimental data from devices with a stack of HfO2 and SiO2 and a stack of HfO2 and oxynidtride was used to verify the model. |  | View paper | | ISBN: | 0-9728422-1-7 |
| Pages: | 600 |
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