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 | MSM 98
Technical Proceedings of the 1998 International Conference on Modeling and Simulation of Microsystems
Chapter 3: Modeling |
| | PSDesigner: A Framework for Transistor Co-Optimization | | Authors: | R. Burch, S. Saxena, P.K. Mozumder, K. Vasanth, J. Davis and S. Rao | | Affilation: | Texas Instruments, Inc., U.S.A. | | Pages: | 76 - 81 | | Keywords: | transistor co-optimization | | Abstract: | One challenge for modern CMOS technology is the manufacture of dissimilar transistors on a sin~le chip at minimum cost. For example, hioh performance transistors for critical paths and low power transistors can be combined to create a hi~h performance chip with reduced power consumption. One approach is to separately design each transistor and duplicate the lithooraphy steps to allow for separate oate oxide, drain extender, channel, etc. Hc~vever, cost concerns require the minimum number of duplicated lithography steps. We have developed a transistor co-optimization methodology and tool, PSDesigner, that can be used to simultaneously design multiple, coupled transistors to meet disparate goals. PSDesigner facilitates the exploration of the costperformance trade-offs that result from duplicatin~ different lithography steps. |  | View paper | | ISBN: | 0-96661-35-0-3 |
| Pages: | 678 |
| Hardcopy: | $100.00 |
| Special: | 3 CD Set — 15% off with Free Shipping |
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