Authors: J. Watts
Affilation: IBM Microelectronics, United States
Pages: 726 - 729
Keywords: compact model, SOI, concurrent design
An important application for partially depleted SOI is high performance microprocessors and other logic chips. In order to deliver market leading performance it is necessary for transistor design and circuit design to be done concurrently. The circuit design process requires a compact model that describes in detail the electrical characteristics of transistors that do not yet exist. Our approach to building such models starts with an existing model that accurately describe a real physical transistor. This model is modified to match key parametric and performance targets for the new transistor. This paper describes a set of physical relationships that can be checked during construction of an SOI compact model to improve the accuracy of the model.