Nanotech 2002 Vol. 1
Nanotech 2002 Vol. 1
Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems

Compact Modeling Chapter 13

How to Build an SOI MOSFET Compact Model without Violating the Laws of Physics

Authors: J. Watts

Affilation: IBM Microelectronics, United States

Pages: 726 - 729

Keywords: compact model, SOI, concurrent design

Abstract:
An important application for partially depleted SOI is high performance microprocessors and other logic chips. In order to deliver market leading performance it is necessary for transistor design and circuit design to be done concurrently. The circuit design process requires a compact model that describes in detail the electrical characteristics of transistors that do not yet exist. Our approach to building such models starts with an existing model that accurately describe a real physical transistor. This model is modified to match key parametric and performance targets for the new transistor. This paper describes a set of physical relationships that can be checked during construction of an SOI compact model to improve the accuracy of the model.


ISBN: 0-9708275-7-1
Pages: 764

2015 & Newer Proceedings

Nanotech Conference Proceedings are now published in the TechConnect Briefs

NSTI Online Community