Nano Science and Technology Institute
Nanotech 2002 Vol. 1
Nanotech 2002 Vol. 1
Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems
Chapter 13: Compact Modeling

Standardization and Validation of Compact Models

Authors:B. Brooks, K. Green, J. Krick, T. Vrotsos and D. Weiser
Affilation:Texas Instruments, US
Pages:653 - 656
Keywords:standardization, validation, compact models
Abstract:The idea of standardizing compact (SPICE-like) models has recently gained momentum in the semiconductor industry. However, since compact model equations reside in software, the concept of standardization is difficult. Several key issues must be addressed, such as accuracy, testing, availability, version control, verification and validation. Most compact models were developed without considering such issues and require productization for the compact model to be useful to the industry. The 1998 SIA Roadmap identified productization as a key issue for 100nm node [1]. With these issues in mind, a group of companies formed the Compact Model Council (CMC), chartered specifically to standardize compact model formulations. The CMC currently has 23 member companies (Table 1), including software vendors and semiconductor suppliers. The current standardization efforts include models for MOSFET (bulk), SOI MOSFET, and Si/SiGe BJT technologies.
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