 | Nanotech 2002 Vol. 1
Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems
Chapter 13: Compact Modeling |
| - | Challenges of Modeling VLSI Interconnects in the DSM Era |
| | N.D. Arora |
| | Simplex Solutions, USA |
| - | Detailed Comparison of the SP2001, EKV, and BSIM3 Models |
| | P. Bendix |
| | LSI Logic, USA |
| - | Standardization and Validation of Compact Models |
| | B. Brooks, K. Green, J. Krick, T. Vrotsos and D. Weiser |
| | Texas Instruments, USA |
| - | Overview of An Advanced Surface-Potential-Based MOSFET Model (SP) |
| | G. Gildenblat and T.L. Chen |
| | Pennsylvania State University, USA |
| - | Engineering BSIM for the Nano-Technology Era and Beyond |
| | M. Chan and C. Hu |
| | Hong Kong University of Science and Technology, Hong Kong |
| - | The Foundations of the EKV MOS Transistor Charge-Based Model |
| | C. Enz, M. Bucher, A.S. Porret, J.M. Sallese and F. Krummenacher |
| | Swiss Center for Electronics and Microtechnology, Switzerland |
| - | The EKV 3.0 Compact MOS Transistor Model: Accounting for Deep-Submicron Aspects |
| | M. Bucher, C. Enz, F. Krummenacher, J.M. Sallese, C. Lallement, A.S. Porret |
| | National Technical University of Athens, Greece |
| - | RF Applications of MOS Model 11 |
| | R. van Langevelde, A.J. Scholten, L.F. Tiemeijer, R.J. Havens and D.B.M. Klaassen |
| | Philips Research Laboratories, The Netherlands |
| - | HiSIM: Self-Consistent Surface-Potential MOS-Model Valid Down to Sub-100nm Technologies |
| | M. Miura-Mattausch, H. Ueno, J.H. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama |
| | Hiroshima University, Japan |
| - | Starting Over: gm/Id-Based MOSFET Modeling as a Basis for Modernized Analog Design Methodologies |
| | D. Foty, D. Binkley and M. Bucher |
| | Gilgamesh Associates, USA |
| - | A Unified Process-Based Compact Model for Scaled PD/SOI and Bulk-Si MOSFETs |
| | J.G. Fossum |
| | University of Florida, USA |
| - | Present Status and Future Direction of BSIM SOI Model for High-Performance/Low-Power/RF Application |
| | S. Fung, P. Su and C. Hu |
| | IBM Microelectronics, USA |
| - | RF MOSFET Noise Parameter Extraction and Modeling |
| | M. Jamal Deen and C-H Chen |
| | McMaster University, Canada |
| - | CMOS RF Modeling and Parameter Extraction Approaches Taking Charge Conservation into Account |
| | M. Je, I. Kwon, J. Han, H. Shin and K. Lee |
| | Korea Advanced Institute of Science and Technology, Korea |
| - | Automatic Generation of RF Compact Models from Device Simulation - Part I: Motivation and methodology |
| | S. Luryi & A. Pacelli |
| | State University of New York at Stony Brook, USA |
| - | Xsim: A Compact Model for Bridging Technology Developers and Circuit Designers |
| | X. Zhou |
| | Nanyang Technological University, Singapore |
| - | Unified Statistical Modeling for Circuit Simulation |
| | C. McAndrew and P.G. Drennan |
| | Motorola, USA |
| - | The Role of TCAD in Compact Modeling |
| | M. Duane |
| | Applied Materials, USA |
| - | Interconnect Modeling for High Speed Digital Circuits - the Role of RLC Coupling |
| | R. Suaya |
| | Mentor Graphics, France |
| - | How to Build an SOI MOSFET Compact Model without Violating the Laws of Physics |
| | J. Watts |
| | IBM Microelectronics, USA |
| - | Methodology for Model Generation with Accuracy from DC to RF |
| | X. Zhang, M. Williams and Z. Liu |
| | Celestry Design Technologies, USA |
| - | Measurements and Modeling of Mobility in Ultra-Thin SOI |
| | M. Mastrapasqua, D. Esseni and C. Fiegna |
| | Agere Systems, USA |
| - | A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) Current Suitable for Compact Modeling |
| | L. Larcher and P. Pavan |
| | Università di Modena e Reggio Emilia, Italy |
| - | Simulation Study of Non-Quasi Static Behaviour of MOS Transistors |
| | D.V. Kumar, R.A. Thakker, M.B. Patil and V.R. Rao |
| | Indian Institute of Technology - Bombay, India |
| - | Compact Model for Manufacturing Design and Fluctuation Study |
| | K.Y. Lim and X. Zhou |
| | Chartered Semiconductor Manufacturing Ltd., Singapore |
| - | Physically-Based Approach to Deep-Submicron MOSFET Compact Model Parameter Extraction |
| | S.B. Chiah, X. Zhou, K.Y. Lim, A. See and L. Chan |
| | Nanyang Technological University, Singapore |
| - | New Compact Model for Generation Drain Current Transients in Weak and Moderate Inversions of Submicron Floating-Body PD SOI MOSFETs |
| | A.M. Ionescu and D. Munteanu |
| | Swiss Federal Institute of Technology (EPFL), Switzerland |
| - | Challenges of Modeling VLSI Interconnects in the DSM Era |
| | N.D. Arora |
| | Simplex Solutions, USA |
| - | Detailed Comparison of the SP2001, EKV, and BSIM3 Models |
| | P. Bendix |
| | LSI Logic, USA |
| - | Standardization and Validation of Compact Models |
| | B. Brooks, K. Green, J. Krick, T. Vrotsos and D. Weiser |
| | Texas Instruments, USA |
| - | Overview of An Advanced Surface-Potential-Based MOSFET Model (SP) |
| | G. Gildenblat and T.L. Chen |
| | Pennsylvania State University, USA |
| - | Engineering BSIM for the Nano-Technology Era and Beyond |
| | M. Chan and C. Hu |
| | Hong Kong University of Science and Technology, Hong Kong |
| - | The Foundations of the EKV MOS Transistor Charge-Based Model |
| | C. Enz, M. Bucher, A.S. Porret, J.M. Sallese and F. Krummenacher |
| | Swiss Center for Electronics and Microtechnology, Switzerland |
| - | The EKV 3.0 Compact MOS Transistor Model: Accounting for Deep-Submicron Aspects |
| | M. Bucher, C. Enz, F. Krummenacher, J.M. Sallese, C. Lallement, A.S. Porret |
| | National Technical University of Athens, Greece |
| - | RF Applications of MOS Model 11 |
| | R. van Langevelde, A.J. Scholten, L.F. Tiemeijer, R.J. Havens and D.B.M. Klaassen |
| | Philips Research Laboratories, The Netherlands |
| - | HiSIM: Self-Consistent Surface-Potential MOS-Model Valid Down to Sub-100nm Technologies |
| | M. Miura-Mattausch, H. Ueno, J.H. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama |
| | Hiroshima University, Japan |
| - | Starting Over: gm/Id-Based MOSFET Modeling as a Basis for Modernized Analog Design Methodologies |
| | D. Foty, D. Binkley and M. Bucher |
| | Gilgamesh Associates, USA |
| - | A Unified Process-Based Compact Model for Scaled PD/SOI and Bulk-Si MOSFETs |
| | J.G. Fossum |
| | University of Florida, USA |
| - | Present Status and Future Direction of BSIM SOI Model for High-Performance/Low-Power/RF Application |
| | S. Fung, P. Su and C. Hu |
| | IBM Microelectronics, USA |
| - | RF MOSFET Noise Parameter Extraction and Modeling |
| | M. Jamal Deen and C-H Chen |
| | McMaster University, Canada |
| - | CMOS RF Modeling and Parameter Extraction Approaches Taking Charge Conservation into Account |
| | M. Je, I. Kwon, J. Han, H. Shin and K. Lee |
| | Korea Advanced Institute of Science and Technology, Korea |
| - | Automatic Generation of RF Compact Models from Device Simulation - Part I: Motivation and methodology |
| | S. Luryi & A. Pacelli |
| | State University of New York at Stony Brook, USA |
| - | Xsim: A Compact Model for Bridging Technology Developers and Circuit Designers |
| | X. Zhou |
| | Nanyang Technological University, Singapore |
| - | Unified Statistical Modeling for Circuit Simulation |
| | C. McAndrew and P.G. Drennan |
| | Motorola, USA |
| - | The Role of TCAD in Compact Modeling |
| | M. Duane |
| | Applied Materials, USA |
| - | Interconnect Modeling for High Speed Digital Circuits - the Role of RLC Coupling |
| | R. Suaya |
| | Mentor Graphics, France |
| - | How to Build an SOI MOSFET Compact Model without Violating the Laws of Physics |
| | J. Watts |
| | IBM Microelectronics, USA |
| - | Methodology for Model Generation with Accuracy from DC to RF |
| | X. Zhang, M. Williams and Z. Liu |
| | Celestry Design Technologies, USA |
| - | Measurements and Modeling of Mobility in Ultra-Thin SOI |
| | M. Mastrapasqua, D. Esseni and C. Fiegna |
| | Agere Systems, USA |
| - | A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) Current Suitable for Compact Modeling |
| | L. Larcher and P. Pavan |
| | Università di Modena e Reggio Emilia, Italy |
| - | Simulation Study of Non-Quasi Static Behaviour of MOS Transistors |
| | D.V. Kumar, R.A. Thakker, M.B. Patil and V.R. Rao |
| | Indian Institute of Technology - Bombay, India |
| - | Compact Model for Manufacturing Design and Fluctuation Study |
| | K.Y. Lim and X. Zhou |
| | Chartered Semiconductor Manufacturing Ltd., Singapore |
| - | Physically-Based Approach to Deep-Submicron MOSFET Compact Model Parameter Extraction |
| | S.B. Chiah, X. Zhou, K.Y. Lim, A. See and L. Chan |
| | Nanyang Technological University, Singapore |
| - | New Compact Model for Generation Drain Current Transients in Weak and Moderate Inversions of Submicron Floating-Body PD SOI MOSFETs |
| | A.M. Ionescu and D. Munteanu |
| | Swiss Federal Institute of Technology (EPFL), Switzerland |
| ISBN: | 0-9708275-7-1 |
| Pages: | 764 |
| Hardcopy: | $100.00 |
| Special: | 3 CD Set — 15% off with Free Shipping |
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