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 | Nanotech 2001 Vol. 1
Technical Proceedings of the 2001 International Conference on Modeling and Simulation of Microsystems
Chapter 4: System Level Modeling |
| | Challenges in CMOS-MEMS Extraction | | Authors: | B. Baidya and T. Mukherjee | | Affilation: | Carnegie Mellon University, U.S.A. | | Pages: | 108 - 111 | | Keywords: | CMOS micromachining, integrated MEMS, extraction, parasitics, canonical representation, layout verification | | Abstract: | CMOS micromachining processes are being increasingly used to fabricate integrated MEMS devices. Verification of such designs requires extraction from layout to mixed domain circuits and MEMS schematics for lumped parameter simulation. The higher etch hole density and multilayer interconnect in CMOS-MEMS designs results in a larger and more complex problem than in polysilicon MEMS. In addition, integrated MEMS verification needs accurate extraction of mechanical and electrical parasitics. This paper reports an extractor with improved scanline-based algorithms to meet the larger problem size associated with integrated CMOS-MEMS layouts. In addition, a hierarchical bin representation is used to store the multilayer electrical connectivity information. A new graph-based algorithm, which reads in an user customizable library file, is used to recognize the wide range of comb drive and spring designs resulting from the flexibility in connectivity. The utility of the extractor is demonstrated using selected designs. |  | View paper | | ISBN: | 0-9708275-0-4 |
| Pages: | 638 |
| Hardcopy: | $100.00 |
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