Nano Science and Technology Institute - NSTI  
Nano Science and Technology Institute   Home | Subscribe | Site Map  
  ABOUT | COURSES | EVENTS | PUBLICATIONS | LEADERSHIP | OUTREACH | NEWS | PRESS | JOBS | Nanotechnology Solutions
px
px fade_top
Publications
Nanotech 2008 CDROM
Nanotech 2007 CDROM
Nanotech 2006 CDROM
Nanotech 2005 CDROM
Nanotech 2004 CDROM
3 CDROM Special Offer
Nanotech 2008 Vol. 1
Nanotech 2008 Vol. 2
Nanotech 2008 Vol. 3
Nanotech 2007 Vol. 1
Nanotech 2007 Vol. 2
Nanotech 2007 Vol. 3
Nanotech 2007 Vol. 4
Nanotech 2006 Vol. 1
Nanotech 2006 Vol. 2
Nanotech 2006 Vol. 3
Nanotech 2005 Vol. 1
Nanotech 2005 Vol. 2
Nanotech 2005 Vol. 3
WCM 2005
Nanotech 2004 Vol. 1
Nanotech 2004 Vol. 2
Nanotech 2004 Vol. 3
Nanotech 2003 Vol. 1
Nanotech 2003 Vol. 2
Nanotech 2003 Vol. 3
Nanotech 2002 Vol. 1
Nanotech 2002 Vol. 2
Nanotech 2001 Vol. 1
Nanotech 2001 Vol. 2
MSM 2000
MSM 99
MSM 98
Index of Authors
Index of Keywords
Index of Affiliations
Library Request Form
Shopping Cart
Order Form
 
Publications Publications
MSM 2000
p
 
Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems
MSM 2000
Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems
 
Chapter 17: Software Tools, CAD Systems
 

Wafer Fabrication Process Simulation Including Cost: Which Should be Used in an In-Line Wafer Inspection Strategy, High Sensitivity and High Cost Inspection Machine or Low Sensitivity and Low Cost Inspection Machine?

Authors:K. Nakamae, S. Yamaji and H. Fujioka
Affilation:Osaka University, Japan
Pages:700 - 703
Keywords:wafer fabrication, inspection process, remedy, sampling inspection, particle
Abstract:By combing an event-driven simulation method including costs and a simple VLSI particle-induced yield predictor, we discuss that which should be used in an in-line wafer inspection strategy, a high sensitivity & high cost inspection machine or a low sensitivity & low cost inspection machine. Two segments of a DRAM fab line including the inspection and the defect sourcing stages are modeled. Simulated results show that setting an adequate wafer rejection condition and selecting a proper sampling plan obtain the minimum cost per chip regardless of the kind of inspection machine.
Wafer Fabrication Process Simulation Including Cost: Which Should be Used in an In-Line Wafer Inspection Strategy, High Sensitivity and High Cost Inspection Machine or Low Sensitivity and Low Cost Inspection Machine?View paper
ISBN:0-9666135-7-0
Pages:741
Hardcopy:$100.00
Special:3 CD Set — 15% off with Free Shipping
Up
nanoPRwire™
nanoPRwire
News Headlines
nano World news
 
 
 
 
px
© Nano Science and Technology Institute     About NSTI | Terms of Use | Privacy Policy | Contact