NSTI Nanotech 2009

2009 Workshop on

Compact Modeling

WCM 2009

May 3 - 7, 2009
George R. Brown Convention Center
Houston, Texas, U.S.A.

Workshop Chair

Xing Zhou Xing Zhou
Professor
Nanyang Technological University, Singapore

Symposium Sessions

 

Monday May 4

8:00 Keynotes: Nanotech & Cleantech & TechConnect
 

Tuesday May 5

8:00 Keynotes: Nanotech & Cleantech & TechConnect
8:30 WCM: Bulk MOS models
10:30 WCM: Bulk/SOI models
1:30 WCM: Multi-gate/nanowire/nanocube models
3:30 WCM: Double-gate models
4:00 POSTERS
 

Wednesday May 6

8:30 WCM: Bulk MOS models
10:30 WCM: Statistical/variation/numerical models
1:30 WCM: RF/noise/capacitance models
1:30 POSTERS
3:30 WCM: Parameter extraction/circuit design
 

Thursday May 7

 

Symposium Program

 

Monday May 4

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8:00 Keynotes: Nanotech & Cleantech & TechConnectTheater AB
 Session chair: Matthew Laudon, NSTI and Patti Glaza, CTSI
8:00 The Nanotech Revolution in Renewable Energy
D. Arvizu - Director, National Renewable Energy Laboratory (NREL), U.S. Department of Energy, US (bio)
8:30 Nanotechnology and the Obama Administration
T. Kalil, Office of Science and Technology Policy, The White House, US
9:00 Innovation for a Secure Future
R. Johnson - CTO, Lockheed Martin, US (bio)
9:30 The Next Big Thing is Really Small
R.J. Kumpf - CAO, Bayer Material Science, US (bio)
 

Tuesday May 5

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8:00 Keynotes: Nanotech & Cleantech & TechConnectTheater AB
 Session chair: Jeff Moseley, Greater Houston Partnership, Shushana Castle, Clinton Global Initiative Member/Millennium Water Alliance, US
8:00 Welcome TechConnect World to Houston
J. Moseley, Greater Houston Partnership, US
8:15 Can Uncle Sam Cure What Ails Clean Tech?
P. Dickerson, HaynesBoone, former COO Office of Energy Efficiency & Renewable Energy, DOE, US (bio)
8:45 Welcome to Houston
B. White, City of Houston, Mayor, US
9:00 Flying into the Future: Continental’s Commitment to the Environment
L. Kellner, Continental Airlines, CEO, US (bio)
9:30 RUSNANO: Driving the Nanotech Industry Growth
A. Chubais, RUSNANO, CEO, RU
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8:30 WCM: Bulk MOS modelsRoom 342 AD
 Session chair: Xing Zhou, Nanyang Technological University, SG
8:30 WCM Keynote: What is a Transistor?
C. Sah, B. Jie, University of Florida, US
9:10 Interface Traps in Surface-Potential-Based MOSFET Models
Z. Chen, X. Zhou, G.H. See, Z. Zhu, G. Zhu, Nanyang Technological University, SG
9:30 Analytic MOSFET Surface Potential Model with Inclusion of Poly-Gate Accumulation, Depletion, and Inversion Effects
Y. Song, J. He, L.N. Zhang, J. Zhang, Peking University, CN
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10:30 WCM: Bulk/SOI modelsRoom 342 AD
 Session chair: Xing Zhou, Nanyang Technological University, SG
10:30 HiSIM-SOI: SOI-MOSFET Model for Circuit Simulation Valid also for Device Optimization
N. Sadachika, S. Kusu, K. Ishimura, T. Murakami, T. Kajiwara, T. Hayashi, Y. Nishikawa, T. Yoshida, M. Miura-Mattausch, Hiroshima University, JP
10:50 Embedded non–volatile memory study with surface potential based model
D. Garetto, A. Zaka, V. Quenette, D. Rideau, E. Dornel, W.F. Clark, M. Minondo, C. Tavernier, Q. Rafhay, R. Clerc, A. Schmid, Y. Leblebici, H. Jaouen, STMicroelectronics, FR
11:10 Dynamic Charge Sharing modeling for surface potential based models
V. Quenette, D. Rideau, R. Clerc, C. Tavernier, H. Jaouen, ST Microelectronics, FR
11:30 Effective Width Modeling for Body-Contacted Devices in Silicon-On-Insulator Technology
S. Khandelwal, E. Tamilmani, K. Shanbhag, J. Watts, IBM SRDC Bangalore, IN
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1:30 WCM: Multi-gate/nanowire/nanocube modelsRoom 342 AD
 Session chair: Bin Jie, Peking University, CN
1:30 Charge-based compact modeling techniques for nanoscale Multi-Gate MOSFETs
B. Iñiguez, F. Lime, A. Lázaro, O. Moldovan, B. Nae, Universitat Rovira i Virgili, ES
1:50 Design study of CNT transistors layouts for high frequency analog circuits
M. Claus, M. Schröter, Technische Universität Dresden, DE
2:10 Analytical Modelling of Ballistic and Quasi-Ballistic Nanowires:Validation and Application to CMOS Architecture
S. Martinie, D. Munteanu, G. Le Carval, M.-A. Jaud, J.L. Autran, CEA, LETI, Minatec, FR
2:30 (CANCELED) MOSFET-Like Carbon Nanotube Field Effect Transistor model
M.T. Ahmadi, Y.W. Heong, R. Ismail, University Technology Malaysia, MY
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3:30 WCM: Double-gate modelsRoom 342 AD
 Session chair: Benjamin Iñiguez, Universitat Rovira i Virgili, ES
3:30 Compact Quantum Modeling Framework for Nanoscale Double-Gate MOSFET
U. Monga, T.A. Fjeldly, Norwegian University of Science and Technology, NO
3:50 Compact Model HiSIM-DG both for Symmetrical and Asymmetrical DG-MOSFET Structures
K. Ishimura, N. Sadachika, S. Kusu, M. Miura-Mattausch, Hiroshima University, JP
4:10 A Unified Compact model for FinFET and Silicon Nanowire MOSFETs
G.J. Zhu, X. Zhou, G.H. See, S.H. Lin, C.Q. Wei, J.B. Zhang, Nanyang Technological University, SG
4:30 Computation Efficient yet Accurate Surface Potential Based Analytic Model for Symmetric DG MOSFETs to Predict Current-Voltage Characteristics
Y. Song, L.N. Zhang, J. Zhang, H. Zhuang, Y.C. Che, J. He, M. Chan, Peking University, CN
4:50 Compact Modeling of Dynamic Threshold Voltage of FinFET High K Gate Stack and Application in Circuit Simulation
F. He, C. Ma, B. Li, L. Zhang, X. Zhang, X. Lin, SZPKU, CN
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4:00 POSTERSExpo Hall
 

Wednesday May 6

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8:30 WCM: Bulk MOS modelsRoom 342 AD
 Session chair: Xing Zhou, Nanyang Technological University, SG
8:30 High-Voltage MOSFET Model Valid for Device Optimization
Y. Oritsuki, T. Sakuda, N. Sadachika, M. Miyake, T. Kajiwara, H. Kikuchihara U. Feldmann, H.J. Mattausch, M. Miura-Mattausch, Hiroshima University, JP
8:50 Compare and Contrast HiSIM-LDMOS and BSIM based compact model of High Voltage MOSFETs for Analog Applications
A. Young, J. Hall, Z. Luo, Y. Xiao, D. Connerney, Fairchild Semiconductor, US
9:10 A Scalable POWER MOSFET Model with an Integrated Body-Diode Including Reverse Recovery
Z. Luo, J. Hall, Y. Xiao, A. Young, R. Carroll, D. Connerney, Fairchild Semiconductor, US
9:30 A PSpice Compact Model for Organic Field-Effect Transistors
C. Ucurum, R.M. Meixner, H. Goebel, Helmut Schmidt University - University of the Federal Armed Forces Hamburg, DE
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10:30 WCM: Statistical/variation/numerical modelsRoom 342 AD
 Session chair: Razali Ismail, Universiti Teknologi Malaysia, MY
10:30 Compact Model Application to Statistical/Probabilistic Technology Variations
X. Zhou, G. Zhu, M. Srikanth, R. Selvakumar, Y. Yan, W. Chandra, J. Zhang, S. Lin, C. Wei, Z. Chen, Nanyang Technological University, SG
10:50 Elements of Statistical SPICE Models
N. Lu, J. Watts, S.K. Springer, IBM, US
11:10 PSP Model Equations Extension for Statistical Estimation of Leakage Current in Nanometer CMOS Technologies Considering Process Variations
C. D’Agostino, P. Flatresse, E. Beigne, M. Belleville, STMicroelectronics, FR
11:30 (CANCELED) Numerical Study of Carrier Velocity for P-type Strained Silicon MOSFET
Y.W. Heong, M.T. Ahmadi, J.E. Suseno, R. Ismail, Universiti Teknologi Malaysia, MY
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1:30 WCM: RF/noise/capacitance modelsRoom 342 AD
 Session chair: Henok Abebe, USC ISI/MOSIS, US
1:30 RF Modeling of 45nm Low-Power CMOS Technology
J. Wang, H. Li, L-H Pan, U. Gogineni, R. Groves, B. Jagannathan, M-H Na, W. Tonti, R. Wachnik, IBM Semiconductor Research and Development Center, US
1:50 Compact Model of Low – Frequency Noise in Nanoscale Metal-Oxide-Semiconductor Field Effect Transistors
D.A. Miller, M.E. Jacob, L. Forbes, Oregon State University, US
2:10 1/f Noise Modeling at Low Temperature with the EKV3 Compact Model
P. Martin, G. Ghibaudo, CEA, LETI, Minatec, FR
2:30 1/f Noise Model for Double-Gate FinFET Biased in Weak Inversion
C-Q Wei, Y-Z Xiong, X. Zhou, Nanyang Technological University, SG
2:50 A Simple, Accurate Capacitance-Voltage Model of Undoped Silicon Nanowire MOSFETs
S. Lin, X. Zhou, G.H. See, G. Zhu, C. Wei, J. Zhang, Z. Chen, Nanyang Technological University, SG
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1:30 POSTERSExpo Hall
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3:30 WCM: Parameter extraction/circuit designRoom 342 AD
 Session chair: Razali Ismail, Universiti Teknologi Malaysia, MY
3:50 SPICE BSIM3 Model Parameters Extraction and Optimization for Low Temperature Application
H. Abebe, V. Tyree, N.S. Cockerham, USC ISI/MOSIS, US
4:10 An SOA Aware MOSFET Model for Highly Integrated, Analog Mixed-Signal Design Environments
J. Hall, Z. Luo, Y. Xiao, A. Young, D. Connerney, Fairchild Semiconductor, US
4:30 Automatically Generated and Experimentally Validated System-Level Model of a Microelectromechanical RF Switch
M. Niessner, G. Schrag, G. Wachutka, J. Iannacci, B. Margesin, Munich University of Technology, DE
 

Synopsis

Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the nanometer system-on-chip (SOC) era.  As the mainstream MOS technology is scaled into the nanometer regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge.

Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together. The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation, which are largely categorized into the following groups:

  • Intrinsic Models
    • Bulk MOSFET
    • Multiple-Gate (MG-FET) - UTB-SOI/double-gate/tri-gate/GAA
    • High-Voltage/LDMOS
    • Schottky-Barrier/Si-nanowire (SB-FET/SiNW)
    • Bipolar/Junction (BJT/HBT/SiGe/JFET)
    • RF/noise
  • Extrinsic/Interconnect Models
    • Parasitic elements
    • Passive device
    • Diode
    • Resistor
    • ESD
    • Interconnect
  • Atomic/Quantum Models
    • Ballistic device
    • Carbon-Nanotube (CNFET)
  • Statistical Models
    • Statistical/process-based
    • Reliability/hot carrier
    • Numerical/TCAD/table-based
  • Model Extraction and Interface
    • Parameter extraction and optimization
    • Model-simulator interface
    • Model standardization

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Keynote

Chih-Tang Sah, "What is a Transistor?

Presentation Slides

Contributed presentation slides. (Click on each  to download the PDF file.  © Copyright of the PDF files belongs to the respective contributors.)

Download and save the entire ZIP file of presentation slides (9MB)
Workshop Program
Z. Chen, Interface Traps in Surface-Potential Based MOSFET Models
V. Quenette, Dynamic Charge Sharing Modeling for Surface Potential Based Models
U. Monga, Compact Quantum Modeling Framework for Nanoscale Double-Gate MOSFET
S. Khandelwal, Effective Width Modeling for BC Devices in SOI
G. Zhu, A Unified Compact Model for FinFET and Silicon Nanowire MOSFETs
C. Ucurum, A PSpice Compact Modelf for Organic Field-effect Transistors
N. Lu, Elements of Statistical SPICE Models
C. D’Agostino, PSP Model Equation Extension for Statistical Estimation of Leakage Current in Nanometer CMOS Technologies Considering Process Variations
P. Martin, 1/f Noise Modeling at Low Temperature with the EKV3 Compact Model
C. Wei, 1/f Noise Model for Double-Gate FinFETs Biased in Weak Inversion
S. Lin, A Simple, Accurate Capacitance-Voltage Model of Undoped Silicon Nanowire MOSFETs
H. Abebe, SPICE BSIM3 Model Parameters Extraction and Optimization for Low Temperature Application
X. Zhou, Compact Model Application to Statistical/Probabilistic Technology Variations

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Web sites for Proceedings

Nanotech 2009, Volume 3, Chapter 9

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