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Program Committee

Conference Proceedings

Conference Technical Proceedings

2006 Workshop on

Compact Modeling

WCM 2006

in Association with

Nineth International Conference on
Modeling and Simulation of Microsystems

MSM 2006

May 9-11, 2006
Hynes Convention Center
Boston, Massachusetts, U.S.A.

Invitees Program Posters Web Sites

Workshop Chair

Xing Zhou Xing Zhou
Professor
Nanyang Technological University, Singapore

Synopsis

Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the nanometer system-on-chip (SOC) era. As the mainstream MOS technology is scaled into the nanometer regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge.

Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together. The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation:

  • Bulk MOS intrinsic models
  • SOI/double-gate/multiple-gate/floating-gate MOS models
  • Bipolar/HBT/SiGe/GaN/JFET models
  • RF/noise/scalable capacitance/NQS models
  • Statistical/predictive/process-based models
  • Interconnection/passive device models
  • Extrinsic/parasitic element models
  • Reliability/hot carrier/tunneling/ESD models
  • Atomic-level/quantum-mechanical compact models
  • Numerical/TCAD/behavioral/table-based models
  • Model parameter extraction and optimization
  • Model-simulator interface and standardization

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Invited Speakers

Invited speakers from all over the world are listed below:

  • Matthias Bucher, Technical University of Crete, Greece
  • Robert Dutton, Stanford University, USA
  • Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland
  • Tor Fjeldly, Norwegian University of Science and Technology, Norway
  • Jerry Fossum, University of Florida, USA
  • Carlos Galup-Montoro, Universidade Federal de Santa Catarina, Brazil
  • Gennady Gildenblat, Pennsylvania State University, USA
  • John Hauser, North Carolina State University, USA
  • Jin He, Peking University, China
  • Chenming Hu and Mohan Dunga, University of California at Berkeley, USA
  • Benjamín Iñíguez, Universitat Rovira i Virgili, Spain
  • Dirk Klaassen, Philips Research Laboratories, The Netherlands
  • Shiuh-Wuu Lee and Sivakumar Mudanai, Intel, USA
  • Juin Liou, University of Central Florida, USA
  • Ramana Malladi, IBM, USA
  • Colin McAndrew, Freescale Semiconductor, USA
  • Mitiko Miura-Mattausch and Tatsuya Ezaki, Hiroshima University, Japan
  • Fabien Prégaldiny, InESS, France
  • Chih-Tang Sah and Bin Jie, University of Florida, USA
  • Michael Schröter, University of Technology Dresden, Germany
  • Ehrenfried Seebacher, Austriamicrosystems AG, Austria
  • Michael Shur, Rensselaer Polytechnic Institute, USA
  • Josef Watts, IBM, USA
  • Man Wong, Hong Kong University of Science and Technology, Hong Kong
  • Yuan Taur, University of California at San Diego, USA
  • Xing Zhou, Nanyang Technological University, Singapore

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Workshop Program

There are 27 invited papers, which are categorized in the following topic areas:

Bulk MOS intrinsic models

  • Carrier Generation and Recombination Currents At Interface Traps In Long-Channel Surface-Potential-Based MOS Transistor Compact Models
    Chih-Tang Sah, University of Florida, US
  • Recent Advances in the EKV3.0 MOSFET Model
    Matthias Bucher, Technical University of Crete, GR
  • Symbolic Charge-based MOSFET Model
    Carlos Galup-Montoro, Universidade Federal de Santa Catarina, BR
  • Theory and Modeling Techniques Used in PSP Model
    Gennady Gildenblat, Pennsylvania State University, US
  • An MOS Model with an Improved Mobility Model
    John Hauser, North Carolina State University, US
  • Benchmark Tests on Conventional Surface Potential Based Charge-Sheet Models and PUNSIM Development
    Jin He, Peking University, CN
  • Accuracy of Long-Channel Surface-Potential-Based MOS Transistor Compact Models
    Bin Jie, University of Florida, US
  • Advanced Compact MOSFET Model HiSIM2 Based Surface Potentials with a Minimum Number of Approximations
    Mitiko Miura-Mattausch, Hiroshima University, JP
  • Halo Doping: Physical Effects and Compact Modeling
    Sivakumar Mudanai, Intel, US
  • Compact Iterative Field Effect Transistor Model
    Michael Shur, Rensselaer Polytechnic Institute, US
  • Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling
    Xing Zhou, Nanyang Technological University, SG

Double/multiple-gate MOS models

  • BSIM4 and BSIM Multi-Gate Progress
    Mohan Dunga, University of California at Berkeley, US
  • A Charge-Based Compact Model of Double Gate MOSFET
    Christian Enz, Swiss Center for Electronics and Microtechnology, CH
  • Precise 2D Compact Modeling of Nanoscale DG MOSFETs Based on Conformal Mapping Techniques
    Tor Fjeldly, Norwegian University of Science and Technology, NO
  • Recent Upgrades and Applications of UFDG
    Jerry Fossum, University of Florida, US
  • DC to RF Small-Signal Compact DG MOSFET Model
    Benjamín Iñíguez, Universitat Rovira i Virgili, ES
  • An Explicit Quasi-static Charge-based Compact Model for Symmetric DG MOSFET
    Fabien Prégaldiny, InESS, FR
  • On the Modeling of the Current-Voltage Characteristics of a Symmetrical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with an Undoped Body
    Man Wong, Hong Kong University of Science and Technology, HK
  • Compact Modeling of Short-channel Double-gate MOSFETs
    Yuan Taur, University of California at San Diego, US

Statistical modeling

  • Device Correlation: Modeling using Uncorrelated Parameters, Characterization Using Ratios and Differences
    Colin McAndrew, Freescale Semiconductor, US
  • Modeling Small MOSFETs Using Ensemble Devices
    Josef Watts, IBM, US

TCAD-based RF models

  • Effects of Scaling on Modeling of Analog RF MOS Devices
    Robert Dutton, Stanford University, US

High-voltage/LDMOS models

  • High-Voltage LDMOS Compact Modeling
    Dirk Klaassen, Philips Research Laboratories, NE
  • Analog Compact Modeling for a 20-120V HV CMOS Technology
    Ehrenfried Seebacher, Austriamicrosystems AG, AT

Interconnect models

  • Compact Modeling of Spiral Inductors for RF Applications
    Juin Liou, University of Central Florida, US

Bipolar/HBT models

  • Development and Design Kit Integration of a Scalable and Statistical High Current Model for Advanced SiGe HBTs
    Ramana Malladi, IBM, US
  • Charge-storage Calculation for Si-based Bipolar Transistors from Device Simulation
    Michael Schröter, University of Technology Dresden, DE

Symposium Sessions

 

Monday May 8

6:00 Poster Session 1 and Nanotech Exhibit Reception hosted by Advance Nanotech, booth #903
 

Tuesday May 9

8:30 WCM 1 - Bulk MOS intrinsic models
10:30 WCM 2 - Bulk MOS intrinsic models
1:30 WCM 3 - Bulk MOS intrinsic models
4:00 WCM 4 - Double/multiple-gate MOS models
4:00 Poster Session 2 and Nanotech Exhibit Reception hosted by Feinstein Kean Healthcare, booth #716
 

Wednesday May 10

8:30 WCM 5 - Double/multiple-gate MOS models
10:30 WCM 6 - Statistical Modeling & TCAD-based Models
1:30 WCM - 7: Poster Briefing 1
2:45 WCM - 8: Poster Briefing 2
4:00 WCM - 9: Poster Briefing 3
6:00 Poster Session 3 and Reception
 WCM - Posters
 

Thursday May 11

8:30 WCM - 10: High-voltage/passive-element models
10:30 WCM 11 - Bipolar/HBT and MOSFET models
 

Symposium Program

  Click on each  to download the PDF file.  © Copyright of the PDF files belongs to the respective contributors.
 

Monday May 8

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6:00 Poster Session 1 and Nanotech Exhibit Reception hosted by Advance Nanotech, booth #903Expo Hall
 

Tuesday May 9

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8:30 WCM 1 - Bulk MOS intrinsic modelsRoom 202
 Session chair: Xing Zhou, Nanyang Technological University, Singapore
8:30 Opening Remarks presentation slides
X. Zhou, Nanyang Technological University, SG
8:30 Carrier Generation and Recombination Currents At Interface Traps in Surface-Potential-Based MOS Transistor Compact Models presentation slides (invited)
C-T Sah and B.B. Jie, University of Florida, US
9:00 Symbolic charge-based MOSFET model presentation slides (invited)
C. Galup-Montoro and M.C. Schneider, Federal University of Santa Catarina, BR
9:30 Theory and Modeling Techniques used in PSP Model presentation slides (invited)
G. Gildenblat, X. Li, H. Wang, W. Wu, A. Jha, R. van Langevelde, A.J. Scholten, G.D.J. Smit and D.B.M. Klaassen, Pennsylvania State University, US
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10:30 WCM 2 - Bulk MOS intrinsic modelsRoom 202
 Session chair: Gennady Gildenblat, Pennsylvania State University, USA
10:30 An Improved MOS Transistor Model with an Integrated Mobility Model presentation slides (invited)
J.R. Hauser, N.C. State University, US
11:00 Benchmark Tests on Conventional Surface Potential Based Charge-Sheet Models And the Advanced PUNSIM Development presentation slides (invited)
J. He, Y. Song, X. Niu, G. Zhang, X. Zhang, R. Huang, M. Chan and Y. Wang, Peking university, CN
11:30 Accuracy of Surface-Potential-Based Long-Wide-Channel MOS Transistor Compact Models presentation slides (invited)
B.B. Jie and C-T Sah, University of Florida, US
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1:30 WCM 3 - Bulk MOS intrinsic modelsRoom 202
 Session chair: Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland
1:30 Advanced Compact MOSFET Model HiSIM2 Based on Surface Potentials with a Minimum Number of Approximation presentation slides (invited)
M. Miura-Mattausch, D. Navarro, N. Sadachika, G. Suzuki, Y. Takeda, M. Miyake, T. Warabino, K. Machida, T. Ezaki, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, R. Inagaki and S. Miyamoto, Hiroshima University, JP
2:00 Halo Doping: Physical Effects and Compact Modeling presentation slides (invited)
S. Mudanai, R. Rios, W-K Shih, P. Packan and S-W Lee, Intel Corp., US
2:30 Compact Iterative Field Effect Transistor Model presentation slides (invited)
M.S. Shur, V. Turin and D. Veksler, T. Ytterdal, B. Iñiguez and W. Jackson, Rensselaer Polytechnic Institute, US
3:00 Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling presentation slides (invited)
X. Zhou, K. Chandrasekaran, S.B. Chiah, W. Shangguan, Z. Zhu, G.H. See, S. Mani Pandey, G.H. Lim, S. Rustagi, M. Cheng, S. Chu and L-C Hsia, Nanyang Technological University, SG
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4:00 WCM 4 - Double/multiple-gate MOS modelsRoom 202
 Session chair: Mitiko Miura-Mattausch, Hiroshima University, Japan
4:00 BSIM4 and BSIM Multi-Gate Progress presentation slides (invited)
M.V. Dunga, C.–H. Lin, X. Xi, S. Chen, D.D. Lu, A.M. Niknejad and C. Hu, UC Berkeley, US
4:30 A Charge-Based Compact Model of Double Gate MOSFET presentation slides (invited)
A.S. Roy, C.C. Enz and J.M. Sallese, CSEM, CH
5:00 Precise 2D Compact Modeling of Nanoscale DG MOSFETs Based on Conformal Mapping Techniques presentation slides (invited)
T.A. Fjeldly, S. Kolberg and B. Iñíguez, Norwegian University of Science and Technology, NO
5:30 Recent Upgrades and Applications of UFDG presentation slides (invited)
J.G. Fossum, V.P. Trivedi, M.M. Chowdhury, S.H. Kim and W. Zhang, University of Florida, US
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4:00 Poster Session 2 and Nanotech Exhibit Reception hosted by Feinstein Kean Healthcare, booth #716Expo Hall
 

Wednesday May 10

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8:30 WCM 5 - Double/multiple-gate MOS modelsRoom 106
 Session chair: Colin McAndrew, Freescale Semiconductor, USA
8:30 DC to RF Small-Signal Compact DG MOSFET model (invited)
B. Iñíguez, A. Lázaro, O. Moldovan, A. Cerdeira and T.A. Fjeldly, Universitat rovira i Virgili (URV), ES
9:00 An Explicit Quasi-Static Charge-Based Compact Model for Symmetric DG MOSFET presentation slides (invited)
F. Prégaldiny, F. Krummenacher, J.-M. Sallese, B. Diagne and C. Lallement, InESS, FR
9:30 On the Modeling of the Current-Voltage Characteristics of a Symmetrical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with an Undoped Body presentation slides (invited)
M. Wong and X. Shi, Hong Kong University of Science and Technology, HK
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10:30 WCM 6 - Statistical Modeling & TCAD-based ModelsRoom 106
 Session chair: Man Wong, Hong Kong University of Science and Technology, Hong Kong
10:30 Device Correlation: Modeling using Uncorrelated Parameters, Characterization Using Ratios and Differences presentation slides (invited)
C.C. McAndrew and P.G. Drennan, Freescale Semiconductor, US
11:00 Modeling Small MOSFETs using Ensemble Devices presentation slides (invited)
J.S. Watts, R. Pino and H. Trombley, IBM, US
11:30 Effects of Scaling on Modeling of Analog RF MOS Devices presentation slides (invited)
Y. Liu, S. Cao, T.Y. Oh, B. Wu, O. Tornblad and R.W. Dutton, Stanford University, US
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1:30 WCM - 7: Poster Briefing 1Room 106
 Session chair: Josef Watts, IBM, USA
1:30 DC and AC Symmetry Tests for MOSFET Models presentation slides
C.C. McAndrew, Freescale Semiconductor, US
1:35 Scalable MOSFET Short-channel Charge Model in All Regions presentation slides
G.H. See, S.B. Chiah, X. Zhou, K. Chandrasekaran, W. Shangguan, Z. Zhu, G.H. Lim, S.M. Pandey, M. Cheng, S. Chu and L-C Hsia, NTU, SG
1:40 Compact Modeling of Nonlinearities in Submicron MOSFETs presentation slides
P.D. da Silva, F.R. de Sousa, C.G. Montoro and M.C. Schneider, Federal University of Santa Catarina, BR
1:45 On the Compact Modelling of Induced Gate Noise in the MOS Transistor presentation slides
A.S. Roy and C.C. Enz, Swiss Federal Institute of Technology, Lausanne (EPFL), CH
1:50 Charge-Based Formulation of Thermal Noise in Short-Channel MOS Transistors presentation slides
V.C. Paim, C. Galup-Montoro and M.C. Schneider, Federal University of Santa Catarina, BR
1:55 Two-Tone Distortion Modeling for SiGe HBTs Using the High-Current Model presentation slides
R.R. Malladi, V. Borich, S.L. Sweeney, J. Rascoe, K.M. Newton, S. Venkatadri, J. Yang and S. Chen, IBM Systems and Technology, US
2:00 BSIM Model for MOSFET Flicker Noise Statistics: Technology Scaling, Area, and Bias Dependence presentation slides
M. Ertürk, R. Anna, K.M. Newton, T. Xia and W.F. Clark, IBM Systems and Technology Group, US
2:05 Investigation of Substrate Current Effects and Modeling of Substrate Resistance Network for RFCMOS presentation slides
J.C. Lee, R.B. Anna, S.L. Sweeney, L.H. Pan and K.M. Newton, IBM Corporation, US
2:10 TCAD-based Process Dependant HSPICE Model Parameter Extraction presentation slides
Y. Mahotin, S. Tirumala, X-W Lin and D. Pramanik, Synopsys, Inc., US
2:15 Analysis and Modeling of NQS Effects in MOSFET’s presentation slides
Y. Ma, M-C Jeng, H. Liang and Z. Liu, Cadence Design Systems, Inc., US
2:20 Compact Capacitance Model of LDMOS for Circuit Simulation presentation slides
Y. Ma, P. Chen, H. Liang, J. Ma, M-C Jeng and Z. Liu, Cadence Design Systems, Inc., US
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2:45 WCM - 8: Poster Briefing 2Room 106
 Session chair: Juin Liou, University of Central Florida, USA
2:45 A Carrier Based Analytic Model for Undoped Surrounding-Gate MOSFETs presentation slides
J. He, X. Zhang, M. Chan and Y. Wang, Peking university, CN
2:50 Compact Modeling of Doped Symmetric DG MOSFETs with Regional Approach presentation slides
K. Chandrasekaran, Z.M. Zhu, X. Zhou, W. Shangguan, G.H. See, S.B. Chiah, S.C. Rustagi and N. Singh, Nanyang Technological University, SG
2:55 Explicit Threshold Voltage Based Compact Model of Independent Double Gate MOSFET presentation slides
M. Reyboz, T. Poiroux, O. Rozeau, P. Martin and J. Jomaah, CEA, FR
3:00 Capacitance Model for Four-Terminal DG MOSFETs presentation slides
T. Nakagawa, T. Sekigawa, T. Tsutsumi, M. Hioki, S. O’uchi and H. Koike, National Institute of Advanced Industrial Science and Technology, JP
3:05 A Computationally Efficient Method for Analytical Calculation of Potentials in Undoped Symmetric DG SOI MOSFET
O. Cobianu and M. Glesner, Darmstadt University of Technology, DE
3:10 Compact Model of drain-current in Double-Gate MOSFETs including carrier quantization and short-channel effects presentation slides
X. Loussier, D. Munteanu, J.L. Autran, S. Harrison and R. Cerutti, L2MP, FR
3:15 Compact modeling and performance analysis of Double-Gate MOSFET-based circuits presentation slides
O. Tintori, D. Munteanu, X. Loussier, J.L. Autran, A. Regnier and R. Bouchakour, L2MP, FR
3:20 Comparison of Three Region Multiple Gate Nanoscale Structures for Reduced Short Channel Effects and High Device Reliability
K. Goel, M. Saxena, M. Gupta and R.S. Gupta, Professor, IN
3:25 Compact Model for Short Channel Effects in Source/Drain Engineered Nanoscale Double Gate (DG) SOI MOSFETs presentation slides
A. Kranti and G.A. Armstrong, Queen’s University of Belfast, UK
3:30 Compact Models for Double Gate and Surrounding Gate MOSFETs presentation slides
H. Abebe, E. Cumberbatch, H. Morris and S. Uno, San Jose State University, US
3:35 SOI CMOS Compact Modeling based on TCAD Device Simulations presentation slides
A. Botula, S. Furkay, D.C. Sheridan, J.M. Johnson and M-H Na, IBM Corporation, US
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4:00 WCM - 9: Poster Briefing 3Room 106
 Session chair: Carlos Galup-Montoro, Universidade Federal de Santa Catarina, Brazil
4:00 On Idlow with Emphasis on Speculative SPICE Modeling presentation slides
Q. Chen, Z-Y Wu, A.B. Icel, J-S Goo, S. Krishnan, C. Thuruthiyil, N. Subba, S. Suryagandh, J.X. An, T. Ly, M. Radwin, J. Yonemura and F. Assad, Advanced Micro Devices, US
4:05 Dynamic Behavior Model for High-k MOSFETs presentation slides
M.V. Dunga, X. Xi, A.M. Niknejad and C. Hu, University of California, Berkeley, US
4:10 A Simple Yet Accurate Mismatch Model For Circuit Simulation presentation slides
Z. Jin, Y-M Lee, J.S. Watts, A.R. Bonaccio, G.J. Schroer and N.G. Pai, IBM, US
4:15 Enhanced Junction Capacitance Modeling presentation slides
F.G. Anderson, R.M. Rassel and M.A. Lavoie, IBM Microelectronics, US
4:20 A Compact Model of Ballistic CNFET for Circuit Simulation presentation slides
B.C. Paul, S. Fujita, M. Okajima and T. Lee, Toshiba America Research Inc., US
4:25 A Circuit-Compatible Model for Ballistic Silicon Nanowire Transistors
J. Chen, Agere Systems, US
4:30 Compact Modeling of Threshold Voltage in Nanoscale Strained-Si/SiGe MOSFETs
S. Nawal, V. Venkataraman and M.J. Kumar, Indian Institute of Technology, IN
4:35 Compact Model Methodology for Dual-Stress Nitride Liner Films in a 90nm SOI ULSI Technology presentation slides
R.Q. Williams, D. Chidambarrao, J.H. McCullen, S. Narasimha, T.G. Mitchell and D. Onsongo, IBM Corporation, US
4:40 A transient circuit model for a phase change memory element presentation slides
H.G.A. Huizing, D. Tio Castro, J.C.J. Paasschens and M.H.R. Lankhorst, Philips, NL
4:45 Static Analog Design Methodology presentation slides
F. Guigues, F. Rudolff and E. Kussener, L2MP UMR 6137 CNRS - ISEN-Toulon, FR
4:50 Interrelations between Threshold Voltage Definitions and Extraction Methods presentation slides
M.C. Schneider, C. Galup-Montoro, M.B. Machado and A.I.A. Cunha, Federal University of Santa Catarina, BR
4:55 A Unified Parameter Extraction Procedure for Scalable Bipolar Transistor Model Mextram presentation slides
H-C Wu, S. Mijalkovic and J.N. Burghartz, Delft university of technology, NL
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6:00 Poster Session 3 and ReceptionHall D
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WCM - PostersHall D
- Improved Basic Symmetry Tests for MOSFET Models
C. McAndrew, Freescale Semiconductor, US
- Scalable MOSFET Short-channel Charge Model in All Regions
G.H. See, S.B. Chiah, X. Zhou, K. Chandrasekaran, W. Shangguan, Z. Zhu, G.H. Lim, S.M. Pandey, M. Cheng, S. Chu and L-C Hsia, NTU, SG
- Compact modeling of nonlinearities in submicron MOSFETs
P.D. da Silva, F.R. de Sousa, C.G. Montoro and M.C. Schneider, Federal University of Santa Catarina, BR
- Charge-Based Formulation of Thermal Noise in Short-Channel MOS Transistors
V.C. Paim, C. Galup-Montoro and M.C. Schneider, Federal University of Santa Catarina, BR
- On the Compact Modelling of Induced Gate Noise in the MOS Transistor
A.S. Roy and C.C. ENz, Swiss Federal Institute of Technology, Lausanne (EPFL), CH
- Low-Frequency and RF Performance of Schottky-Diode for RFIC Applications and the Observation of RTS Noise Characteristics
Y.Z. Xiong, G.Q. Lo, J.L. Shi, M.B. Yu, W.Y. Loh and D.L. Kwong, Institute of Microelectronics, Singapore, SG
- Two-Tone Distortion Modeling for SiGe HBTs Using the High-Current Model
R. Malladi, V. Borich, S.L. Sweeney, J. Rascoe, K.M. Newton, S. Venkatadri, J. Yang and S. Chen, IBM Systems and Technology, US
- BSIM Model for MOSFET Flicker Noise Statistics: Technology Scaling, Area, and Bias Dependence
M. Erturk, R. Anna, J.C. Lee, L.H. Pan, J.R. Jones, K.M. Newton, T. Xia and C.J. LaMothe, IBM Systems and Technology Group, US
- Investigation of Substrate Current Effects and Modeling of Substrate Resistance Network for RFCMOS
J.C. Lee, R.B. Anna, L.H. Pan and K.M. Newton, IBM Corporation, US
- NQS Effects in MOSFET’s and its Implementation in Advanced Compact Models
Y. Ma, M-C Jeng and Z. Liu, Cadence Design Systems, Inc., US
- Capacitance Modeling for LDMOS
Y. Ma, P. Chen, M-C Jeng and Z. Liu, Cadence Design Systems, Inc., US
- A Carrier Based Analytic Model for Undoped Surrounding-Gate MOSFETs
J. He, Z. Xing, G. Zhang and Y. Wang, Peking university, CN
- Compact Modeling of Doped Symmetric DG MOSFETs with Regional Approach
Z.M. Zhu, K. Chandrasekaran, X. Zhou, S. Wangzuo, S.G. Huei, C.S. Ben, S.C. Rustagi and N. Singh, Nanyang Technological University, SG
- Explicit Compact Model of Independent Double Gate MOSFET
M. Reyboz, O. Rozeau, T. Poiroux, P. Martin and J. Jomaah, cea, FR
- Capacitance Model for Four-Terminal DG MOSFETs
T. Nakagawa, T. Sekigawa, T. Tsutsumi, M. Hioki, S. O’uchi, H. Koike, National Institute of Advanced Industrial Science and Technology, JP
- A Computationally Efficient Method for Analytical Calculation of Potentials in Undoped Symmetric DG SOI MOSFET
O. Cobianu and M. Glesner, Darmstadt University of Technology, DE
- Compact Model of Drain-Current in Double-Gate MOSFETs including carrier quantization and short-channel effects
X. Loussier, D. Munteanu, J.L. Autran, S. Harrison and R. Cerutti, L2MP, FR
- Performance analysis of Double-Gate MOSFET-based circuits using a compact model implemented in Eldo IC analog simulator
O. Tintori, X. Loussier, D. Munteanu, J.L. Autran, A. Regnier and R. Bouchakour, L2MP, FR
- Comparison of Three Region Multiple Gate Nanoscale Structures for Reduced Short Channel Effects and High Device Reliability
K. Goel, M. Saxena, M. Gupta and R.S. Gupta, University of Delhi South Campus, IN
- Compact Model for Short Channel Effects in Source/Drain Engineered Nanoscale Double Gate (DG) SOI MOSFETs
A. Kranti and G.A. Armstrong, Queen’s University of Belfast, UK
- Compact Models for Double Gate and Surrounding Gate MOSFETs
H. Abebe, E. Cumberbatch, H. Morris and S. Uno, San Jose State University, US
- On Idlow with Emphasis on Speculative SPICE Modeling
Q. Chen, Z-Y Wu, A.B. Icel, J-S Goo, S. Krishnan, C. Thuruthiyil, N. Subba, S. Suryagandh, J.X. An, T. Ly, M. Radwin, J. Yonemura and F. Assad, Advanced Micro Devices, US
- Dynamic Behavior Model for High-K MOSFETs
M.V. Dunga, X. Xi, A.M. Niknejad and C. Hu, University of California, Berkeley, US
- A simple yet accurate mismatch model for circuit simulation
Z. Jin, Y-M Lee, J. Watts, A. Bonaccio, G. Schroer and N. Pai, IBM, US
- Enhanced Junction Depletion Capacitance Modeling
F.G. Anderson, R.M. Rassel and M.A. Lavoie, IBM Microelectronics, US
- A Compact Model of Ballistic CNFET for Circuit Simulation
B.C. Paul, S. Fujita, M. Okajima and T. Lee, Toshiba America Research Inc., US
- A Circuit-Compatible Model of Ballistic Silicon Nanowire Transistors
J. Chen, Agere Systems, US
- Compact Modeling of Threshold Voltage in Nanoscale Strained-Si/SiGe MOSFETs
S. Nawal, V. Venkataraman and M.J. Kumar, Indian Institute of Technology, New Delhi, IN
- Compact Model Methodology for Dual-Stress Nitride Liner Films in a 90nm SOI ULSI Technology
R.Q. Williams, D. Chidambarrao, J.H. McCullen, S. Narasimha, T.G. Mitchell and D. Onsongo, IBM Corporation, US
- A transient lumped element model for a phase change circuit memory element
H.G.A. Huizing, D. Tio Castro, J.C.J. Paasschens and M.H.R. Lankhorst, Philips, NL
- STATIC ANALOG DESIGN METHODOLOGY
F. Guigues, F. Rudolff and E. Kussener, L2MP UMR 6137 CNRS - ISEN-Toulon, FR
- Interrelations between threshold voltage definitions and extraction methods
M.C. Schneider, C. Galup-Montoro, M.B. Machado and A.I.A. Cunha, Federal University of Santa Catarina, BR
- A Unified Parameter Extraction Procedure for Scalable Bipolar Transistor Model Mextram
H-C Wu, S. Mijalkovic and J.N. Burghartz, Delft university of technology, NL
- TCAD-based Process Dependant HSPICE Model Parameter Extraction
Y. Mahotin and S. Tirumala, Synopsys, Inc., US
- SOI CMOS Compact Modeling based on TCAD Device Simulations
A. Botula, S. Furkay, D.C. Sheridan, J.M. Johnson and M-H Na, IBM Corporation, US
 

Thursday May 11

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8:30 WCM - 10: High-voltage/passive-element modelsRoom 105
 Session chair: Michael Schroter, University of Technology Dresden, Germany
8:30 High-Voltage LDMOS Compact Modeling presentation slides (invited)
M.B. Willemsen, R. van Langevelde and D.B.M. Klaassen, Philips Research, NL
9:00 Analog Compact Modeling for a 20-120V HV CMOS Technology presentation slides (invited)
E. Seebacher, W. Posch, K. Molnar and Z. Huszka, austriamicrosystems AG, AT
9:30 Compact Modeling of Spiral Inductors for RF Applications presentation slides (invited)
J. Chen and J.J. Liou, University of Central Florida, US
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10:30 WCM 11 - Bipolar/HBT and MOSFET modelsRoom 105
 Session chair: Dirk Klaassen, Philips Research Laboratories, the Netherlands
10:30 Development and Design Kit Integration of a Scalable and Statistical High Current Model for Advanced SiGe HBTs presentation slides(invited)
R.M. Malladi, K.M. Newton and M.S. Schroter, IBM Systems and Technology, US
11:00 Charge-storage calculation for Si-based bipolar transistors from device simulation presentation slides (invited)
M. Schröter and H. Tran, UCSD, US
11:30 Compact Modeling of Short Channel Double-Gate MOSFETs (invited)
H. Lu, X. Liang, W. Wang and Y. Taur, Univ. California, San Diego, US
12:00 Recent Advances in the EKV3.0 MOSFET Model presentation slides (invited)
M. Bucher, A. Bazigos, E. Kitonaki, F. Krummenacher, Technical University of Crete, GR
 

Poster Session

Poster presentations in the scope of “compact models for circuit simulation” are solicited. Please note that only posters submitted to WCM will be considered. For accepted poster papers, a 5-minute oral briefing for each poster is planned before the poster presentation session.

Contributed presentation slides can be downloaded from the “slide-icon” link above

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Web Sites

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Presentation Slides

Contributed presentation slides can be downloaded from the “slide-icon” link above.

save Download and save the entire ZIP file of presentation slides (27 MB). (© Copyright of the PDF files belongs to the respective contributors.  Last update: August 5, 2006.)

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Websites for Proceedings

http://www.nsti.org/procs/Nanotech2006v3/7

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Web Site Archive

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